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still cause interrupts. Interrupts for correctable read data errors should
also be disabled, as read errors will result from not correcting the single-
bit errors in data that gets written into memory.
Disabling correctable write data errors involves setting <CWDD> in the
TLCNR register of all nodes in the system. The <CWDD> bit tells all
nodes to disable asserting TLSB_DATA_ERROR on correctable write data
errors. Commander nodes must also provide a means to disable any other
actions they would normally take to inform the data requester of the error,
which is usually an interrupt to a CPU.
Error detection is not disabled. Error bits will still set in the CSR registers
of all nodes that detect correctable data errors. A CPU may poll these CSR
registers to see if the errors are still occurring. If an uncorrectable data
error occurs, the status registers are overwritten and the requester gets in-
terrupted.
Double-bit error interrupts cannot be disabled.
2-46 TLSB Bus
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