Table of Contents
Advertisement
the write must be reissued by the DECchip 21164 to the TLSB as a Write
Block.
In the case that the Set Dirty bit is held off by an invalidate to the block,
the Set Dirty request is reissued as a Read-Miss-Modify.
To perform a write to a shared block, DECchip 21164 issues a Write Block
request. The CPU module arbitrates for and acquires the bus before ac-
knowledging the Write Block. By acquiring the TLSB before acknowledg-
ing the Write Block command, the write is guaranteed to be completed in
order.
To do STxC to a shared location, the DECchip 21164 issues a Write Block
Lock request. This command is not acknowledged until the CPU module
receives TLSB_CMD_ACK indicating that the write will be accepted.
Writes to TLMBPRx are not ACKed in the event that the I/O cannot accept
a new I/O request, and the lack of TLSB_CMD_ACK must cause the STxC
to fail and be retried again later. The retry mechanism is under software
control. The failure is communicated to the DECchip 21164 through the
signal CFAIL.
4.2.10 Memory Barriers
Memory barriers issued by the DECchip 21164 cause an entry in the CPU
module cache control queue of events to the DECchip 21164 to be tagged
with a memory barrier indicator. The DECchip 21164 is not acknowledged
until this indicator has reached the top of the queue and indicates that all
events that occurred prior to the memory barrier have completed.
4.3 Main Memory
The TLSB memory module provides up to 2 Gbytes of dynamic random ac-
cess memory (DRAM) to the CPU. A subsystem with seven memory mod-
ules provides a total of 14 Gbytes of memory. The TLSB memory subsys-
tem features the following:
TLSB memory modules run synchronous with the TLSB. Memory transac-
tions are initiated by commanders on the command/address bus. Memory
data transfers are initiated over a separate 256-bit data bus. All transac-
tions on the data bus are retired in the order in which they were received
on the command/address bus.
• 128-Mbyte to 2-Gbyte memory capacity per module
• Incremental configuration to a maximum of seven modules imple-
mented on extended-hex +1" size boards in a dual-processor Al-
phaServer 8400 system
• 2-, 4-, and 8-way interleaving
• 64-byte block transfers, executed in two 32-byte transfers over two con-
tiguous data cycles
• Memory modules with DRAM arrays of 1M x 4 or 4M x 4 components
• Read and write data wrapping on 32-byte naturally aligned boundaries
• Quadword ECC protection that allows detection of single-bit, 2-bit, and
complete 4-bit DRAM failures.
Memory Subsystem 4-9
Advertisement
Table of Contents
