I/O Port Generated Error Interrupts - DEC AlphaServer 8200 Technical Manual

Therefore, when an interrupt occurs on an I/O bus (that is, XMI, Future-
bus+, or PCI), the I/O bus adapter must first acquire the interrupt vector
for that interrupt. On the Futurebus+ and the PCI, the vector is acquired
as part of the INTR transaction. On the XMI bus, the vector is acquired
using an IDENT transaction. If the interrupt was a WE (write error)
IVINTR, the XMI adapter module uses a predefined vector instead of exe-
cuting an IDENT.
Once the I/O bus adapter acquires the IDENT vector from the interrupting
I/O device, it sends an INTR/IDENT packet to the I/O port over the Up
Hose. The INTR/IDENT packet includes the vector and IPL of the inter-
rupt.
Only one interrupt at a time may be posted by an I/O bus adapter at a
given IPL from a single hose interconnect.
The I/O port loads the vector into the appropriate TLILIDx register and
generates an interrupt to one or more CPUs by writing to the appropriate
I/O interrupt register (TLIOINTRx) in TLSB broadcast space. The I/O port
selects the appropriate TLIOINTRx based on its node ID. For example an
I/O port as node 8 writes to TLIOINTR8, node 7 to TLIOINTR7, and so on.
The CPU(s) targeted for the interrupt are determined from the CPU Inter-
rupt Mask Register (TLCPUMASK) in the I/O port. The IPL received
from the hose interconnect and the 16-bit CPU mask field of the TLCPU-
MASK register are written to the CPU's TLIOINTRx register. This allows
interrupts to be targeted to any or all of the CPUs.
Upon receiving the interrupt request, one of the targeted CPUs reads the
appropriate I/O port's Interrupt Levelx IDENT register (TLILIDx) corre-
sponding to the I/O port that requested the interrupt and the requested
IPL level, causing the appropriate I/O port to return the vector for the
posted interrupt. Other targeted CPUs may either notice the relevant
read to that I/O port's TLILIDx register and take a passive release or may
execute their own read of TLILIDx. If another interrupt at the relevant
level is pending, the additional CPU read of TLILIDx returns that IDENT
vector. If no other interrupts are pending at the given level, the I/O port
returns zeros, forcing the CPU to take a passive release.
After one of the CPUs targeted by the interrupt reads the appropriate I/O
port's TLILIDx register, that I/O port sends an INTR/IDENT Status Re-
turn packet to the I/O bus adapter module over the Down Hose. The arri-
val of the INTR/IDENT Status Return packet at the I/O bus adapter tells
it that it can service another interrupt at that IPL, thus providing inter-
rupt transaction flow control.
6.3.3.2

I/O Port Generated Error Interrupts

The I/O port generates an interrupt when it detects an error condition.
Possible errors include Up Hose parity, packet content, and packet length.
The I/O port also detects and reports violations of the hose flow control
(that is, buffer count overflows or underflows). The I/O port also reports
errors related to accessing the TLSB.
I/O port generated error interrupts work in the same manner as remote
bus interrupts with the following exceptions:
• I/O port generated error interrupts always interrupt on IPL 17.
I/O Port 6-9