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supports one Turbo Vortex bus (Turbo Vortex Bus A) and two hose buses:
internal hose (Hose 0) and external hose (Hose 1).
The integrated I/O section contains all the hardware that connects from
the internal hose, including the two HPC (hose to PCI) gate arrays, to all
the SCSI, Ethernet, and FDDI and NVRAM daughter cards (Figure 6-35).
The integrated I/O section is a logically separate I/O subsystem connected
to the integrated I/O port interface through the internal hose.
The KFTIA is compatible in architecture to other PCI I/O allowing soft-
ware drivers to run with no modifications. The KFTIA supports a 32K-
entry scatter/gather address map that is used to translate PCI memory ad-
dresses into main memory addresses. To improve the individual DMA
transaction performance, the KFTIA implements an on-chip scatter/gather
cache, and reads of a full host memory block. To improve overall DMA
throughput, the KFTIA implements two physically separate PCI buses and
allows a DMA operation to be pending simultaneously for each bus.
KFTIA also supports the protocol required to receive Memory Channel
writes. This allows NVRAM on the PCI to be kept consistent with main
memory. The integrated I/O port supports Memory Channel writes down
the Down Hose.
The KFTIA interfaces the TLSB bus to any one of three different I/O bus
adapter modules through the external hose. The three I/O adapter mod-
ules are the XMI adapter (DWLMA), the Futurebus+ adapter (DWLAA),
and the PCI bus adapter (DWLPA).
The integrated I/O section is connected to the TLSB bus interface by the
internal hose (Hose 0). The internal hose is identical in operation and pro-
tocol to the external hose. It is different electrically, as there are no driv-
ers and receivers needed to drive and receive the hose cable.
6.8.1 Integrated I/O Section
The integrated I/O section communicates with the integrated I/O port
through Hose 0 (the internal hose). Refer to the documents listed below for
detailed description and discussions of the various components of the inte-
grated I/O section.
Figure 6-35 shows a block diagram of the integrated I/O section of the
KFTIA.
6-80 I/O Port
• DWLPA PCI Adapter Technical Manual: Describes the hose to PCI
(HPC) gate array and related hardware. The hose to PCI interface
that is implemented on the integrated I/O port is a subset of what is
implemented on the DWLPA.
• Ethernet Controller 21040 (TULIP) Engineering Specification: De-
scribes the Ethernet chip. Consult also the DEC 21040 Typical
Motherboard Implementation.
• ISP 1020 Intelligent SCSI Processor Technical Manual
• DEFPZ Hardware Specification
• ITIOP (KFTIA) NVRAM Specification
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