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3.3.2 I/O Space
The I/O space contains the I/O window space, TLSB CSR space, module
Gbus space, and DECchip 21164 private CSR space. It is selected when bit
<39> is one.
3.3.2.1
I/O Window Space
This space, defined by addresses in the range 80 0000 0000 to DF FFFF
FFC0 is used for PCI bus addressing. I/O window space support is dis-
cussed in Section 3.4.
3.3.2.2
TLSB CSR Space
All TLSB CSR registers (except TLMBPRx) are 32 bits wide and aligned
on 64-byte boundaries. (TLMBPR registers are 38 bits wide.) System vis-
ible registers are accessed using CSR read and write commands on the
bus.
Figure 3-3 shows how TLSB CSR space is divided.
Figure 3-3
TLSB CSR Space Map
Each CPU module on the TLSB is assigned 64K CSR locations to imple-
ment the TLSB required registers (errors registers, configuration registers,
and so on). In addition, a 64K broadcast region is defined, where all mod-
ules accept writes without regard to module number.
3-8 CPU Module
Byte Address
FF 8000 0000
FF 87FF FFC0
FF 8800 0000
FF 883F FFC0
FF 8840 0000
FF 887F FFC0
FF 8A00 0000
FF 8A3F FFC0
FF 8A40 0000
FF 8DFF FFC0
FF 8E00 0000
FF 8E3F FFC0
FF 8E40 0000
FF 8FFF FFC0
Reserved
Node 0 CSRs: 64K CSR Locations
Node 1 CSRs: 64K CSR Locations
. . .
Node 8 CSRs: 64K CSR Locations
Reserved
Broadcast Space: 64K CSR Locations
Reserved
BXB-0780-94
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