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TLEPDERR—DIGA Error Register
Address
BB + 1540
Access
R/W
The TLEPDERR register contains CPU module error bits. These
bits are set as a result of errors detected in the MMG or any of the
DIGA chips. This register resides in DIGA0.
31
RSVD
GBTO: Gbus Timeout Error
D2DCPE0: DIGA to DIGA CSR Parity Error #0
A2DCPE: ADG to DIGA CSR Parity Error
3
2
1
0
BXB-0503-93
System Registers 7-57
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