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The TLSB memory is designed to operate within the following TLSB clock
cycle times:
To support operating at multiple cycle times while maintaining low latency
and high bandwidth, the DSMs are designed as variable-length state ma-
chines with multiple taps for controlling external events. To keep DRAM
cycle times to a minimum, the primary DRAM control signal timing has
selectable timing edges that follow the selection of the TLSB clock cycle.
Another attribute of the CTL is that there are three copies of address and
control for each memory bank to keep delays and skews to a minimum.
5.1.3 Address/RAS Decode Logic
The address/RAS decode logic determines the allocation of TLSB addresses
to DRAM row and column addresses. It also handles the module selection
process when system-level interleaving is invoked.
5.1.3.1
128MB/512MB Memory Module Addressing
Table 5-2 shows how the TLSB addresses are allocated for a two-string
memory module. As shown, RAS_SEL<1:0> is not affected by addresses in
this case since there is only one string per bank (it is always 00).
• Write
• Refresh
• 10.0 to 11.299 ns
• 11.3 to 12.999 ns
• 13.0 to 15.0 ns (Memory can operate at cycle times as slow as 30 ns us-
ing power-up default settings without violating the DRAM refresh re-
quirements.)
Memory Interface 5-5
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