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Write Bank Unlock
Used by the I/O port to complete a Read-Modify-Write. Writes the data
specified by the address and bank number and unlocks the bank.
CSR Read
Read the CSR location specified by the address. Bank number specifies a
CPU virtual ID.
CSR Write
Write the CSR location specified by the address. Bank number specifies a
CPU virtual ID.
2.2.7 Data Bus Concepts
The TLSB transfers data in the sequence order that valid address bus com-
mands are issued. The rule for gaining access to the data bus is as follows.
When the sequence count reaches the sequence number for which a slave
interface wishes to transfer data, the data bus belongs to the slave. The
sequencing of the data bus is controlled by the slave node that was ad-
dressed in the address bus command. The exception to this rule is the
CSR broadcast write, where the commander is responsible for data bus se-
quencing.
To cycle the bus through a data sequence, the slave node drives the con-
trol signals and monitors the shared and dirty status lines. The shared
and dirty status lines are driven by the CPU nodes. Shared and dirty per-
mit all nodes to perceive the state of the cache block that is being trans-
ferred. Section 2.2.8.9 and Section 2.2.8.10 describe the effects of shared
and dirty on data transfers. Depending on the transaction type and the
status of dirty, either a CPU, the transaction commander, or the slave
drives data on the bus. Table 4-3 describes the TLSB actions in detail.
Moving shared and dirty status to the data bus sequence decreases the
load on a critical timing path. The path to look up the cache Duplicate Tag
Store (DTag) and have status ready still has conditions under which CPUs
might not be ready to return status when the slave node is ready for data
transfer. In addition, once the data transaction starts it cannot be halted
and the receiving node must consume the data. The protocol provides a
flow control mechanism to permit the bus to be held pending all nodes be-
ing ready to transmit valid cache block status and to drive or receive the
data.
2.2.7.1
Data Bus Sequencing
Data bus transfers take place in the sequence that the address bus com-
mands were issued. When a valid data transfer command is issued, the
commander and slave nodes tag the current sequence count and pass the
sequence number to the data bus interface.
2.2.7.2
Hold
If a device is not ready to respond to the assertion of TLSB_SEND_DATA,
either because it does not yet know the shared and dirty state of the block
in its cache, or because data buffers are not available to receive or send the
data, it drives TLSB_HOLD to stall the transaction.
2-18 TLSB Bus
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