DEC AlphaServer 8200 Technical Manual page 231

Table 7-4 TLBER Register Bit Definitions (Continued)
Name Bit(s)
<0>
ATCE
Type Function
W1C, 0 Address Transmit Check Error.
CPU: Set when a transmit check error is de-
tected on the TLSB_ADR<39:3>,
TLSB_ADR_PAR, TLSB_BANK_NUM<3:0>,
TLSB_CMD<2:0>, or TLSB_CMD_PAR signals.
This is a system fatal error that asserts
TLSB_FAULT. When this bit is set, <ATDE> is
also set.
Memory: Not implemented.
I/O: Set when a transmit check error is de-
tected on the TLSB_ADR<39:5>,
TLSB_ADR_PAR, TLSB_BANK_NUM<3:0>,
TLSB_CMD<2:0>, or TLSB_CMD_PAR signals.
This is a system fatal error that asserts
TLSB_FAULT. When this bit is set, <ATDE> is
also set.
System Registers 7-13