Tlmmrn-Memory Mapping Registers; Tlmmrn Register Bit Definitions - DEC AlphaServer 8200 Technical Manual

TLMMRn—Memory Mapping Registers
Address BB + 0200 to BB + 03C0
Access W (CPU), R/W (I/O)
The TLMMRn registers contain the mapping information for per-
forming bank decode.
30
31
RSVD
VALID
Table 7-7

TLMMRn Register Bit Definitions

Name Bit(s)
VALID <31>
<30:26>
RSVD
<25:12>
ADDRESS
<11>
SBANK
26 25
ADDRESS
Type Function
CPU, W, 0 Valid. When set, indicates that the mapping
I/O, R/W, 0 register is valid and can be used in address de-
coding. <VALID> is set only if a corresponding
memory bank ID has been written to a memory
controller.
CPU, W, 0 Reserved. Must be written as zero.
I/O, R/W, 0
CPU, W, 0 Address. Bank address range to be decoded.
I/O, R/W, 0 This field is compared to the physical address
lines TLSB_ADR<39:26>.
CPU, W, 0 Single Bank. Set to define a single bank num-
I/O, R/W, 0 ber determined by the register number n.
Cleared to define two bank numbers, n and n+8.
This bit should be set when defining a bank
number for a single-bank module.
12 11 10 9 8 7
6
INTLV ADRMSK
SBANK
RSVD
INTMASK
System Registers 7-21
4
5 3 2 1 0
BXB-0757-93