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Table 7-61 IDPDR0–3 Register Bit Definitions (Continued)
Name
FRC_VAL_SEQ_ERR
FRC_DN_DPE
FRC_CSR_BUS_APE
FRC_CSR_BUS_DPE
RSVD
FRC_ECC<7:0>
Bit(s)
Type
Function
<19>
R/W, 0
Force Down Valid Sequence Error. When
set, forces VALID to be asserted for an extra
cycle for down Turbo Vortex Mailbox Command
packets.
<18>
R/W, 0
Force Down Data Parity Error. When set,
forces bad parity on the down Turbo Vortex bus
as it exits the IDR. This bit can be set inde-
pendently in each IDR to force bad parity in dif-
ferent longwords.
<17>
W, 0
Force CSR Bus Address Parity Error. This
bit forces an address parity error in the selected
IDR chip on the CSR address bus. The error is
detected as IDPNSE<IDR_CSR_BUS_PE> in
the IDR in which the error was forced. Refer to
Table 7-62. This bit automatically clears after a
CSR read or CSR write to the I/O port.
<16>
R/W, 0
Force CSR Bus Data Parity Error. This bit
forces a data parity error from the IDR0 chip on
the CSR data bus between IDR0 and the ICR
and other IDRs. The error is detected at the
ICR and IDR1:3 chips. Refer to Table 7-62.
<15:8>
R/W, 0
Reserved. Read as zeros.
<7:0>
R/W, 0
Force ECC<7:0>. When set, these bits flip the
corresponding ECC check bits. Setting one of
these bits causes a single-bit error when the I/O
port drives read return data on the TLSB. Set-
ting two of these bits at the same time cause a
double-bit error when the I/O port drives read
return data on the TLSB.
FRC_ECC<0> flips ECC check bit 0,
FRC_ECC<1> flips ECC check bit 1, and so on.
System Registers 7-135
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