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2.2.2 Virtual Node Identification
TLSB system operation requires that certain functional units can be iden-
tified uniquely, independent of their physical location. Specifically, individ-
ual memory banks and CPUs must be uniquely addressable entities at the
system level. As multiple memory banks and CPUs are implemented on
single modules, a physical node ID is insufficient to uniquely address each
bank or each CPU. The AlphaServer 8400/8200 systems, therefore, employ
virtual node IDs, software-generated, dynamically stored IDs, to identify
its functional units. Note that CSR addresses are still managed on a node
basis within the system and are keyed off the physical node ID.
Virtual node IDs are set by writing the TLVID register fields with the
value required. The console is responsible for initializing the values at
power-up. A module can have multiple virtual node IDs associated with it;
for example, dual CPUs or memory controllers with multiple memory
banks. The maximum number of virtual IDs per TLSB module is eight.
The unused ID fields are not implemented, and a CSR read must return 0
in the unused fields. Virtual node IDs are identified by the type of module
they reside on. They are:
2.2.3 Address Bus Concepts
The TLSB implements separate address and data buses. The purpose of
the address bus is to signal a bus node (usually memory) with an address
so that it can transfer data as soon as possible. The TLSB uses the mem-
ory bank to control flow of addresses on the bus. Once a bank has been
addressed and it is busy, no other commander can use that bank until it
becomes free. An analysis of memory latency showed that the following
actions in the address propagation path directly contribute to latency:
The TLSB attempts to address these issues to create a low latency system.
All memory is divided into banks. A bank is addressed by a unique 4-bit
bank number transmitted on the TLSB address bus. The CPU always has
to perform a bank decode to decide if it can issue the request. Therefore,
the CPU transmits the bank number along with the address and command
on the address bus. A compare of the bank's virtual ID to the transmitted
bank number is performed in the memory bank controller. This simplifies
the memory address decoding and permits fast memory addressing.
On a TLSB CPU module a tag lookup and compare is permitted to take
place in parallel with bus arbitration. When the CPU performs a tag
probe, it passes a valid signal to the CPU memory interface to indicate
that the current address is being used in a cache lookup. This valid signal
can be used to initiate a bus request and gain early access to the address
bus. This means that a cache tag lookup that hits in the cache can poten-
tially perform a request and win the bus. By the time the CPU has to
2-6 TLSB Bus
• CPUID, range 0–15
• MEMID, range 0–15. This corresponds to the memory bank number
MEM_BANKn (n = 0 to 15).
• Cache tag lookup and compare
• Check for bank busy
• Bus arbitration
• Address bank decode in the memory
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