Serial Rom Port; Directly Addressable Console Hardware - DEC AlphaServer 8200 Technical Manual

Communications to the UARTs, FEPROMs, watch chip, LED control regis-
ters, and other registers are accomplished over the 8-bit wide Gbus.

3.2.1 Serial ROM Port

Each DECchip 21164 chip provides a serial interface that allows the inter-
nal I-cache to be loaded serially from FEPROM following a reset. This al-
lows bootstrap code to execute before anything else on the module is tested
or required. Both DECchip 21164s are loaded from a common area of
FEPROM in parallel. The MMG sequences FEPROM accesses and per-
forms parallel to serial conversion of the FEPROM data.
Each DECchip 21164 has its I-cache loaded with a section of console code
that allows for DECchip 21164 testing and initialization and provides a
means to cause the balance of diagnostic and console code to be loaded
from the FEPROMs over the Gbus.
The DECchip 21164 also provides bits in the internal processor registers
(IPRs) that allow this serial interface to be used as a general purpose 1-bit
wide I/O port. A simple UART or more elaborate interface can be config-
ured, all under software control.

3.2.2 Directly Addressable Console Hardware

Table 3-1 summarizes the implementation of the directly addressable
hardware in the processor's Gbus space. Refer to the TurboLaser EV5
Dual-Processor Module Specification for a detailed discussion of the con-
sole hardware and the operation of its various components.
• A set of module-level parallel I/O ports for functions such as LED
status indicators and node identification
• Two serial I/O ports connected to the serial ROM I/O of the DECchip
21164's for manufacturing diagnostic use
• Support for serial number loading
CPU Module 3-5