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Figure 6-11
Minimum Latency Mode
WIN or LOSE
or PREQ<n>
Note that NEXT_REQ_HI<n> would have become asserted in cycle 6 even
if the I/O port did not request the bus in cycles 3–6. This happens because
cycle 3 was considered a "potential request" cycle whether a TLSB node as-
serted its request in cycle 3 or not. As a result, if the I/O port were not to
request the TLSB until cycle 7 or later, it would be done using
TLSB_REQ8_HIGH.
Figure 6-12
Minimum Latency Mode Timing Example
BANK _AVL <n>
REQ8_LOW
REQ8_HIGH
NEXT_REQ_HI<n>
(toggle flop)
Toggle 50% High/50% Low Mode
This mode allows an I/O port in node 8 to toggle between TLSB_REQ8_
HIGH and TLSB_REQ8_LOW when arbitrating for the TLSB. When the
I/O port wins the bus for a given bank, it toggles the corresponding flop so
that the next arbitration for that bank is performed at the alternate re-
quest level. If the I/O port loses arbitration while using TLSB_REQ8_
LOW to vie for the TLSB bus, the I/O port switches to TLSB_REQ8_
HIGH. There is a minimum of four cycles before the I/O port switches to
TLSB_REQ8_HIGH to allow the look-back-two logic to resolve any "false"
arbitrations that may have delayed a "real" arbitration from getting the
bus. The I/O port always uses TLSB_REQ8_ HIGH when arbitrating for
6-32 I/O Port
RESET
REQ8_HIGH
ELSE
WIN
REQ8_LOW
ELSE
1
2
3
Notes:
WIN = (GRANT* - NOP)
LOSE = (REQ8_LOW * PREQ<n>*-WIN)
PREQ<n>(potential request) =
(-ARB_SUPPRESS*
-BANK_AVL<n>*
-REQ8_HIGH*
-ARB_CYCLE)
4
5
6
7
BXB0811.AI
8
9
BXB0800.AI
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