Iccdr Register Bit Definitions - DEC AlphaServer 8200 Technical Manual

Table 7-57 ICCDR Register Bit Definitions
Name Bit(s)
<31>
ENA_DMA_HID
<30:9>
RSVD
<8>
FRC_IDR_CMD_PE
<7>
RSVD
<6>
FRC_BNK_BSY
<5>
FRC_CMD_PE
Type Function
R/W, 0 Enable DMA Hose ID. When set and the I/O
port is hard-wired to enable debug mode, the
number of the hose that originated the transac-
tion is inserted at address bits <26:25> for mem-
ory transactions (that is, A<28>=0). This bit is
only valid when the I/O port is hard-wired to en-
able debug mode. Otherwise, the bit has no ef-
fect on I/O port operation.
R/W, 0 Reserved. Must be zero.
W, 0 Force IDR CMD Parity Error. When set,
forces a parity error on all four CMD buses going
from the ICR to the IDRs. It should cause the
IDPNSE<IDR_CMD_PE> bit in each of the IDRs
to set. This error causes the I/O port to assert
TLSB_FAULT.
R/W, 0 Reserved. Must be zero.
W, 0 Force Bank Busy Error. When set, inverts
the CSR_BANK_BUSY signal in the ICR. A
CSR access to the I/O port while this bit is set
causes TLBER<BAE> to set. This error causes
the I/O port to drive TLSB_FAULT. This bit will
automatically clear after the I/O port detects
TLER<BAE>.
R/W, 0 Force Command Parity Error. When set,
forces the ICR to assert bad parity on the TLSB
during a command cycle driven by the I/O port.
System Registers 7-123