Rx Margin Analysis; Functional Description; Horizontal Eye Margin Scan - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
Table 4-25: RX Clock Divider Control Attributes (Cont'd)
Attribute
RXRECCLK_CTRL
TRANS_TIME_RATE

RX Margin Analysis

Functional Description

As line rates and channel attenuation increase, the receiver equalizers are often enabled to
overcome channel attenuation. This posts a challenge to system debug as the quality of the
link cannot be determined by measuring the far-end eye diagram. At high line rates, the
received eye measured on the printed circuit board can appear to be completely closed
even though the internal eye after the receiver equalizer is open.
The RX CDR block provides a diagnostic mechanism to estimate the receiver eye margin
after the equalizer when in the 1x divider setting (RXPLL_DIVSEL_OUT = 1).

Horizontal Eye Margin Scan

In the regular operational mode where RX_EYE_SCANMODE is set to 00, the CDR
decision making state machine centers the edge sampler to the data transition region. The
phase of the data sampler has a constant 0.5 UI offset from the edge sampler to allow the
data sampler to stay in the middle of the data eye.
In the horizontal eye margin scan mode where RX_EYE_SCANMODE is set to 10, the CDR
allows the user to control the phase offset between the data sampler and the edge sampler
via the attribute RX_EYE_OFFSET. This is illustrated in
machine operates normally, the scanned margin is the true receiver margin, incorporating
both receiver equalizer and CDR effects. Refer to
on the DFE.
At the beginning of a horizontal eye margin scan, the CDR state machine should be frozen
because measuring the bit error ratio (BER) requires sampling the equalized waveform far
from the optimal points. This sampling could cause CDR errors, resulting in slipped cycles
and inducing unrecoverable, high error rates. (The requirement to freeze the CDR carries
the penalty that the input RX data must be synchronous to the RX REFCLK.) The CDR can
be frozen by setting the lowest 11 bits of the PMA_RX_CFG attribute to zero
(PMA_RX_CFG[10:0] = 11'b0).
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210
Type
String This attribute is the multiplexer select signal shown in
determines which GTX transceiver internal clock is output to fabric via
RXRECCLK signal port. Valid settings are:
"RXRECCLKPCS"
"RXRECCLKPMA_DIV1"
"RXRECCLKPMA_DIV2"
"RXPLLREFCLK_DIV1"
"RXPLLREFCLK_DIV2"
8-bit Reserved. Use only recommended values from the Virtex-6 PGA GTX
Hex Transceiver Wizard.
This attribute determines when PHYSTATUS and RXRATEDONE are
asserted after a rate change.
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Description
Figure
Figure 4-16. As the CDR state
RX Equalizer, page 194
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
4-15. It
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