Rx Margin Analysis - Xilinx Virtex UltraScale+ FPGAs User Manual

Table 56: RX Fabric Clock Output Control Ports
Port
CH[0/1]_RXOUTCLKSEL[2:0]
CH[0/1]_RXOUTCLK
CH[0/1]_RXPROGDIVCLK
RXRECCLK[0/1]

RX Margin Analysis

As line rates and channel attenuation increase, the receiver equalizers are more often enabled to
overcome channel attenuation. This poses a challenge to system bring-up because the quality of
the link cannot be determined by measuring the far-end eye opening at the receiver pins. At high
line rates, the received eye measurement on the printed circuit board can appear to be
completely closed even though the internal eye after the receiver equalizer is open.
Because the GTM receiver is ADC-based, the conventional eye scan used in the previous family
of transceivers (such as GTH and GTY transceivers) is not possible. The GTM RX provides a
sampled eye diagram that can be used to measure and visualize the receiver signal margin after
the equalizer, as shown in the following figure.
Figure 42:
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In
Out
Out
Out
Sampled Eye Diagram for (a) PAM4 and (b) NRZ Modulation
Async This port must be set to 3'b000.
Clock Reserved.
Clock RXPROGDIVCLK is the parallel output clock from
the RX programmable divider. This clock is the
recommended output to the interconnect logic
through BUFG_GT.
Clock RXRECCLK is the same as RXPROGDIVCLK, and it
can be routed to the MGTREFCLK output pad.
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Chapter 4: Receiver
Description
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