Freeze Data Cache; Enable Data Cache; Instruction Burst Enable; Clear Instruction Cache - Motorola MC68030 User Manual

On-Chip Cache Memories
6.3.1.5 FREEZE DATA CACHE. Bit 9, the FD bit, is set to freeze the data cache. When the
FD bit is set and a miss occurs during a read or write of the data cache, the indexed entry
is not replaced. However, write cycles that hit in the data cache cause the entry to be
updated even when the cache is frozen. When the FD bit is clear, a miss in the data cache
during a read cycle causes the entry (or line) to be filled, and the filling of entries on writes
that miss are then controlled by the WA bit. A reset operation clears the FD bit.
6.3.1.6 ENABLE DATA CACHE. Bit 8, the ED bit, is set to enable the data cache. When it
is cleared, the data cache is disabled. A reset operation clears the ED bit. The supervisor
normally enables the data cache, but it can clear ED for system debugging or emulation, as
required. Disabling the data cache does not flush the entries. If it is enabled again, the
previously valid entries remain valid and can be used.
6.3.1.7 INSTRUCTION BURST ENABLE. Bit 4, the IBE bit, is set to enable burst filling of
the instruction cache. Operating systems and other software set this bit when burst filling of
the instruction cache is desired. A reset operation clears the IBE bit.
6.3.1.8 CLEAR INSTRUCTION CACHE. Bit 3, the CI bit, is set to clear all entries in the
instruction cache. Operating systems and other software set this bit to clear instructions from
the cache prior to a context switch. The processor clears all valid bits in the instruction cache
at the time a MOVEC instruction loads a one into the CI bit of the CACR. The CI bit is always
read as a zero.
6.3.1.9 CLEAR ENTRY IN INSTRUCTION CACHE. Bit 2, the CEI bit, is set to clear an
entry in the instruction cache. The index field of the CAAR (see Figure 6-15) corresponding
to the index and long-word select portion of an address specifies the entry to be cleared.
The processor clears only the specified long word by clearing the valid bit for the entry at the
time a MOVEC instruction loads a one into the CEI bit of the CACR, regardless of the states
of the EI and FI bits. The CEI bit is always read as a zero.
MOTOROLA MC68030 USER'S MANUAL 6-17