E.1.1.3.3 Condition Register Crn Field—Compare Instruction - Motorola MPC8240 User Manual

Table E-1. Bit Settings for CR0 Field of CR (Continued)
CR0 Bit
2
3
E.1.1.3.2 Condition Register CR1 Field Definition
The bit settings for the CR1 field are shown in Table E-2.
CR1 Bit
4
5
6
7
E.1.1.3.3 Condition Register CRn Field—Compare Instruction
For a compare instruction the bits of the specified field are interpreted as shown in
Table E-3.
Table E-3. CRn Field Bit Settings for Compare Instructions
1
CRn Bit
0 Less than or floating-point less than (LT, FL).
For integer compare instructions: rA < SIMM or rB (signed comparison) or
rA < UIMM or rB (unsigned comparison).
For floating-point compare instructions: frA < frB.
1 Greater than or floating-point greater than (GT, FG).
For integer compare instructions: rA > SIMM or rB (signed comparison) or
rA > UIMM or rB (unsigned comparison).
For floating-point compare instructions: frA > frB.
2 Equal or floating-point equal (EQ, FE).
For integer compare instructions: rA = SIMM, UIMM, or rB.
For floating-point compare instructions: frA = frB.
3 Summary overflow or floating-point unordered (SO, FU).
For integer compare instructions:This is a copy of the final state of XER[SO]
at the completion of the instruction.
For floating-point compare instructions: One or both of frA and frB is a Not a
Number (NaN).
1
Notes: Here, the bit indicates the bit number in any one of the 4-bit subfields, CR0–CR7.
Zero (EQ)—This bit is set when the result is zero.
Summary overflow (SO)—This is a copy of the final state of XER[SO] at
the completion of the instruction.
Table E-2. Bit Settings for CR1 Field of CR
Floating-point exception (FX)—This is a copy of the final state of
FPSCR[FX] at the completion of the instruction.
Floating-point enabled exception (FEX)—This is a copy of the final
state of FPSCR[FEX] at the completion of the instruction.
Floating-point invalid exception (VX)—This is a copy of the final state
of FPSCR[VX] at the completion of the instruction.
Floating-point overflow exception (OX)—This is a copy of the final state
of FPSCR[OX] at the completion of the instruction.
Appendix E. Processor Core Register Summary
Description
Description
Description
PowerPC Register Set
E-5