Segment Register Manipulation Instructions (Oea); Translation Lookaside Buffer Management Instructions-(Oea) - Motorola MPC750 User Manual

2.3.6.3.2 Segment Register Manipulation Instructions (OEA)
The instructions listed in Table 2-59 provide access to the segment registers for 32-bit
implementations. These instructions operate completely independently of the MSR[IR] and
MSR[DR] bit settings. Refer to "Synchronization Requirements for Special Registers and
for Lookaside Buffers," in Chapter 2, "PowerPC Register Set," of The Programming
Environments Manual for serialization requirements and other recommended precautions
to observe when manipulating the segment registers.
Table 2-59. Segment Register Manipulation Instructions
Name Mnemonic Syntax Implementation Notes
Move to Segment Register mtsr
SR,rS
-
Move to Segment Register Indirect mtsrin rS,rB
-
Move from Segment Register mfsr rD,SR The shadow SRs in the instruction MMU can be read
by setting HIDO[RISEG] before executing mfsr.
Move from Segment Register Indirect mfsrin rD,rB
-
2.3.6.3.3 Translation Lookaside Buffer Management Instructions-(OEA)
The address translation mechanism is defined in terms of the segment descriptors and page
table entries (PTEs) PowerPC processors use to locate the logical-to-physical address
mapping for a particular access. These segment descriptors and PTEs reside in segment
registers and page tables in memory, respectively.
See Chapter 7, "Memory Management," for more information about TLB operations.
Table 2-60 summarizes the operation of the TLB instructions in the MPC750.
Table 2-60. Translation Lookaside Buffer Management Instruction
Name
Mnemonic
Syntax
Implementation Notes
TLB tlbie rB Invalidates both ways in both instruction and data TLB entries at the index
Invalidate provided by EA[14-19].lt executes regardless of the MSR[DR] and MSR[IR]
Entry settings.To invalidate all entries in both TLBs, the programmer should issue 64
tlbie instructions that each successively increment this field.
TLB tlbsync
-
On the MPC750, the only function tlbsync serves is to wait for the TLBISYNC
Synchronize
signal to go inactive.
Implementation Note-The tibia instruction is optional for an implementation if its
effects can be achieved through some other mechanism. Therefore, it is not implemented
on the MPC750. As described above, tlbie can be used to invalidate a particular index of
the TLB based on EA[14-19]-a sequence of 64 tlbie instructions followed by a tlbsync
instruction invalidates all the TLB structures (for EA[14-l9]
=
0, 1,2'00.,63). Attempting
to execute tibia causes an illegal instruction program exception.
Chapter 2. MPC750 Processor Programming Model 2-67