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Architecture
5.2.4.9.4 OE/RE: Output Enable / Read Enable Signal Control Assertion / Deassertion Time
(OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
The GPMC_CONFIG4_i[3-0] OEONTIME field (where i = 0 to 7) defines the OE_RE signal assertion
time relative to start access time. It is applicable only to read accesses.
The GPMC_CONFIG4_i[12-8] OEOFFTIME field defines the OE_RE signal deassertion time relative to
start access time. It is applicable only to read accesses. OE_RE is not asserted during a write cycle.
OEONTIME, OEOFFTIME, OEAADMUXONTIME and OEAADMUXOFFTIME parameters are
applicable to synchronous and asynchronous modes. OEONTIME can be used to control an address
and byte enable valid setup time control before OE_RE assertion. OEOFFTIME can be used to control
an address and byte enable valid hold time control after OE_RE assertion.
OEAADMUXONTIME and OEAADMUXOFFTIME parameters have the same functions as OEONTIME
and OEOFFTIME, but apply to the first OE assertion in the AAD-multiplexed protocol for a read phase,
or to the only OE assertion for a write phase. It is the user responsibility to make sure
OEAADMUXOFFTIME is programmed to a value lower than OEONTIME. Functionality in AAD-mux
mode is undefined if the settings do not comply with this requirement. OEAADMUXOFFTIME shall
never be equal to OEONTIME because the AAD-mux protocol requires a second address phase with
the OE signal de-asserted before OE can be asserted again to define a read command.
The OE_RE signal transitions as controlled through OEONTIME, OEOFFTIME, OEAADMUXONTIME
and OEAADMUXOFFTIME can be delayed by half a GPMC_FCLK period by enabling the
GPMC_CONFIG4_i[7] OEEXTRADELAY bit. This half of a GPMC_FCLK period provides more
granularity on OE_RE assertion and deassertion time to assure proper setup and hold time relative to
GPMC_CLK. If enabled, OEEXTRADELAY applies to all parameters controlling OE_RE transitions.
OEEXTRADELAY must be used carefully, to avoid control-signal overlap between successive accesses
to different chip-selects. This implies the need to program RDCYCLETIME and WRCYCLETIME to be
greater than OE_RE signal-deassertion time, including the extra half-GPMC_FCLK-period delay.
When the GPMC generates a read access to an address-/data-multiplexed device, it drives the address
bus until OE assertion time.
5.2.4.9.5 WE: Write Enable Signal Control Assertion / Deassertion Time (WEONTIME / WEOFFTIME /
WEEXTRADELAY)
The GPMC_CONFIG4_i[19-16] WEONTIME field (where i = 0 to 3) defines the WE signal-assertion
time relative to start access time. The GPMC_CONFIG4_i[28-24] WEOFFTIME field defines the WE
signal-deassertion time relative to start access time. These bit fields only apply to write accesses. WE
is not asserted during a read cycle.
WEONTIME can be used to control an address and byte enable valid setup time control before WE
assertion. WEOFFTIME can be used to control an address and byte enable valid hold time control after
WE assertion.
WE signal transitions as controlled through WEONTIME, and WEOFFTIME can be delayed by half a
GPMC_FCLK period by enabling the GPMC_CONFIG4_i[23] WEEXTRADELAY bit. This half of a
GPMC_FCLK period provides more granularity on WE assertion and deassertion time to guaranty
proper setup and hold time relative to GPMC_CLK. If enabled, WEEXTRADELAY applies to all
parameters controlling WE transitions.
The WEEXTRADELAY bit must be used carefully to avoid control-signal overlap between successive
accesses to different chip-selects. This implies the need to program the WRCYCLETIME bit field to be
greater than the WE signal-deassertion time, including the extra half-GPMC_FCLK-period delay.
576
General-Purpose Memory Controller (GPMC)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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