Table of Contents
Advertisement
Registers
5.5.4 GPMC_IRQSTATUS
This interrupt status register regroups all the status of the module internal events that can generate an
interrupt.
31
15
Reserved
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-10 Reserved
9
WAIT1EDGEDETECTIONSTATUS
8
WAIT0EDGEDETECTIONSTATUS
7-2
Reserved
1
TERMINALCOUNTSTATUS
0
FIFOEVENTSTATUS
666
General-Purpose Memory Controller (GPMC)
Preliminary
Figure 5-54. GPMC_IRQSTATUS
10
R-0
2
R-0
Table 5-59. GPMC_IRQSTATUS Field Descriptions
Value Description
R0
W0
R1
W1
R0
W0
R1
W1
R0
W0
R1
W1
R0
W0
R1
W1
© 2011, Texas Instruments Incorporated
Reserved
R-0
9
WAIT1EDGE
DETECTIONSTATUS
R/W-0
1
TERMINAL
COUNTSTATUS
R/W-0
0
Reserved
Status of the Wait1 Edge Detection interrupt
A transition on WAIT1 input pin has not been detected
WAIT1EDGEDETECTIONSTATUS bit unchanged
A transition on WAIT1 input pin has been detected
WAIT1EDGEDETECTIONSTATUS bit is reset
Status of the Wait0 Edge Detection interrupt
A transition on WAIT0 input pin has not been detected
WAIT0EDGEDETECTIONSTATUS bit unchanged
A transition on WAIT0 input pin has been detected
WAIT0EDGEDETECTIONSTATUS bit is reset
0
Reserved
Status of the TerminalCountEvent interrupt
Indicates that CountValue is greater than 0
TERMINALCOUNTSTATUS bit unchanged
Indicates that CountValue is equal to 0
TERMINALCOUNTSTATUS bit is reset
Status of the FIFOEvent interrupt
Indicates than less than GPMC_PREFETCH_STATUS[16]
FIFOTHRESHOLDSTATUS bytes are available in prefetch mode
and less than FIFOTHRESHOLD bytes free places are available in
write-posting mode.
FIFOEVENTSTATUS bit unchanged
Indicates than at least GPMC_PREFETCH_STATUS[16]
FIFOTHRESHOLDSTATUS bytes are available in prefetch mode
and at least FIFOTHRESHOLD bytes free places are available in
write-posting mode.
FIFOEVENTSTATUS bit is reset
www.ti.com
16
8
WAIT0EDGE
DETECTIONSTATUS
R/W-0
0
FIFOEVENT
STATUS
R/W-0
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
