Texas Instruments TMS320C6A816 Series Technical Reference Manual page 673

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Table 5-66. GPMC_CONFIG1_i Field Descriptions (continued)
Bit Field
22 WAITREADMONITORING
21 WAITWRITEMONITORING
20 Reserved
19-18 WAITMONITORINGTIME
17-16 WAITPINSELECT
15-14 Reserved
13-12 DEVICESIZE
11-10 DEVICETYPE
9-8 MUXADDDATA
7-5 Reserved
4 TIMEPARAGRANULARITY
3-2 Reserved
SPRUGX9 – 15 April 2011
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Preliminary
Value Description
Selects the Wait monitoring configuration for Read accesses (Reset value is
BOOTWAITEN input pin sampled at IC reset)
0 WAIT pin is not monitored for read accesses
1 WAIT pin is monitored for read accesses
Selects the Wait monitoring configuration for Write accesses
0 WAIT pin is not monitored for write accesses
1 WAIT pin is monitored for write accesses
0 Reserved
Selects input pin Wait monitoring time
0 WAIT pin is monitored with valid data
1h WAIT pin is monitored one GPMC_CLK cycle before valid data
2h WAIt pin is monitored two GPMC_CLK cycle before valid data
3h Reserved
Selects the input WAIT pin for this chip select (Reset value is
BOOTWAITSELECT input pin sampled at IC reset for CS0 and 0 for CS1-7)
0 WAIT input pin is WAIT0
1h WAIT input pin is WAIT1
2h Reserved
3h Reserved
0 Reserved
Selects the device size attached (Reset value is BOOTDEVICESIZE input
pin sampled at IC reset for CS[0] and 01 for CS[1-7])
0 8 bit
1h 16 bit
2h Reserved
3h Reserved
Selects the attached device type
0 NOR Flash like, asynchronous and synchronous devices
1h Reserved
2h NAND Flash like devices, stream mode
3h Reserved
Enables the Address and data multiplexed protocol (Reset value is
CS0MUXDEVICE input pin sampled at IC reset for CS[0] and 0 for CS[1-7])
0 Non-multiplexed attached device
1h AAD-multiplexed protocol device
2h Address and data multiplexed attached device
3h Reserved
0 Reserved
Signals timing latencies scalar factor (Rd/WRCycleTime, AccessTime,
PageBurstAccessTime, CSOnTime, CSRd/WrOffTime, ADVOnTime,
ADVRd/WrOffTime, OEOnTime, OEOffTime, WEOnTime, WEOffTime,
Cycle2CycleDelay, BusTurnAround, TimeOutStartValue)
0 ×1 latencies
1 ×2 latencies
0 Reserved
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Registers
673