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Introduction
4.1
Introduction
4.1.1 Purpose of the Peripheral
The general-purpose interface combines two general-purpose input/output (GPIO) banks. Each GPIO
module provides 32 dedicated general-purpose pins with input and output capabilities; thus, the
general-purpose interface supports up to 64 (2 × 32) pins. These pins can be configured for the
following applications:
•
Data input (capture)/output (drive)
•
Keyboard interface with a debounce cell
•
Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations.
4.1.2 Features
Each channel in the GPIO module has the following features:
•
The output enable register (GPIO_OE) controls the output capability for each pin.
•
The output line level reflects the value written in the data output register (GPIO_DATAOUT) through
the peripheral bus.
•
The input line can be fed in to the GPIO module through an optional and configurable debouncing
cell.
•
The input line value is sampled into the data input register (GPIO_DATAIN) and can be read from
the peripheral bus.
•
In Active mode, the input line can be used through level and edge detectors to trigger synchronous
interrupts. The edge (rising, falling, or both) or the level (logical 0, logical 1, or both) to be used can
be configured.
The global features of the GPIO module are:
•
Two identical interrupt generation sub-modules process synchronous interrupt requests from each
channel in order to be used independently in a bi-processor environment. Each sub-module controls
its own synchronous interrupt request line and has its own interrupt enable and interrupt status
registers. The interrupt enable register (GPIO_IRQSTATUS_SET_x) selects the channel(s)
considered for the interrupt request generation, and the interrupt status register
(GPIO_IRQSTATUS_RAW_x) determines which channel(s) has/have activated the interrupt request.
Event detection on GPIO channels is reflected into the interrupt status registers independently from
the interrupt enable registers content.
The module provides an alternative to the atomic 'Test and Set' operations for the data output and
interrupt enable registers. For these registers, the module implements the "Set and Clear protocol
register update".
528
General-Purpose I/O (GPIO) Interface
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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