Nor Interfacing Timing Parameters Diagram - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Basic Programming Model
5.3.6 GPMC Timing Parameters
Figure 5-43 shows a programming model diagram for the NOR interfacing timing parameters.
Table 5-41 lists bit fields to configure adequate timing parameter in various memory modes.
640
General-Purpose Memory Controller (GPMC)
Preliminary
Figure 5-43. NOR Interfacing Timing Parameters Diagram
Asynchronous
write
Asynchronous
write
operation
Synchronous
read
Synch
read
operation
© 2011, Texas Instruments Incorporated
Start
Synchronous
Type write
of access?
No Write Access
Synchronous
write
operation
Asynchronous
read
Type
of access?
No read access
ronous Asynch ronous
read
operation
End
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SPRUGX9 – 15 April 2011
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