Gpmc Clocks; Gpmc_Config1_I Configuration; Gpmc Local Power Management Features - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
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Architecture
5.2.4.1
GPMC Clock Configuration
Table 5-6
describes the GPMC clocks.
Signal
GPMC_FCLK
GPMC_CLK
The GPMC_CLK is generated by the GPMC from the internal GPMC_FCLK clock. The source of the
GPMC_FCLK is described in
GPMCFCLKDIVIDER field (for i = 0 to 3) as shown in
Source Clock
GPMC_FCLK
5.2.4.2
GPMC Software Reset
The GPMC can be reset by software through the GPMC_SYSCONFIG[1] SOFTRESET bit. Setting the
bit to 1 enables an active software reset that is functionally equivalent to a hardware reset. Hardware
and software resets initialize all GPMC registers and the finite state-machine (FSM) immediately and
unconditionally. The GPMC_SYSSTATUS[0] RESETDONE bit indicates that the software reset is
complete when its value is 1. The software must ensure that the software reset completes before doing
GPMC operations.
5.2.4.3
GPMC Power Management
GPMC power is supplied by the CORE power domain, and GPMC power management complies with
system power-management guidelines.
the GPMC module.
Feature
Clock Auto Gating
Slave Idle Modes
Clock Activity
Master Standby Modes
Global Wake-up Enable
Wake-up Sources Enable
560
General-Purpose Memory Controller (GPMC)
Preliminary
Table 5-6. GPMC Clocks
I/O
Description
I
Functional and interface clock
O
External clock provided to synchronous external memory devices.
Table
5-4. The GPMC_CLK is configured via the GPMC_CONFIG1_i[1-0]
Table 5-7. GPMC_CONFIG1_i Configuration
GPMC_CONFIG1_i[1-0]
GPMCFCLKDIVIDER
00
01
10
11
Table 5-8
Table 5-8. GPMC Local Power Management Features
Registers
GPMC_SYSCONFIG[0]
AUTOIDLE] bit
GPMC_SYSCONFIG[4-3]
SIDLEMODE bit field
N/A
N/A
N/A
N/A
© 2011, Texas Instruments Incorporated
Table
5-7.
GPMC_CLK Generated Clock
Provided to External Memory Device
GPMC_FCLK
GPMC_FCLK/2
GPMC_FCLK/4
GPMC_FCLK/8
describes power-management features available for
Description
This bit allows a local power optimization inside the module, by
gating the GPMC_FCLK clock upon the internal activity.
Force-idle, No-idle and Smart-idle wakeup modes are available
Feature not available
Feature not available
Feature not available
Feature not available
www.ti.com
SPRUGX9 – 15 April 2011
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