Emac Control Module Miscellaneous Interrupt Status Register (Cmmiscintstat); Emac Control Module Miscellaneous Interrupt Status Register (Cmmiscintstat) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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3.3.1.12 EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT)

The miscellaneous interrupt status register (CMMISCINTSTAT) is shown in
in Table 3-22.
Figure 3-23. EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-22. EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT)
Bit Field
31-4 Reserved
3-0 C_MISC_STAT
SPRUGX9 – 15 April 2011
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Preliminary
Reserved
R-0
Field Descriptions
Value Description
0 Reserved
0-Fh Core 0 Misc Masked Interrupt Status.
Each bit in this register corresponds to the miscellaneous interrupt (STAT_PEND, HOST_PEND,
MDIO_LINKINT, MDIO_USERINT) that is enabled and generating an interrupt on
C0_MISC_PULSE.
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Reserved
R-0
Registers
Figure 3-23 and described
4 3
C_MISC_STAT
R/W-0
EMAC/MDIO Module
16
0
463