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When the GPMC generates a write access to an AAD-multiplexed device, all address bits are driven
onto the address/data bus in two separate phases. The first phase is used for the MSB address and is
qualified with OE driven low. The second phase for LSB address is qualified with OE driven high. The
address phase ends at WE assertion time.
The CS and DIR signals are controlled in the same way as for synchronous single read operation on an
address/data-multiplexed device.
•
Address valid signal ADV is asserted and deasserted twice during a read transaction
– ADV first assertion time is controlled by the GPMC_CONFIG3_i[6-4] ADVAADMUXONTIME
field.
– ADV first deassertion time is controlled by the GPMC_CONFIG3_i[26-24]
ADVAADMUXRDOFFTIME field.
– ADV second assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field.
– ADV second deassertion time is controlled by the GPMC_CONFIG3_i[12-8] ADVRDOFFTIME
field.
•
Output Enable signal OE is asserted and deasserted twice during a read transaction (OE second
assertion indicates a read cycle)
– OE first assertion time is controlled by the GPMC_CONFIG4_i[6-4] OEAADMUXONTIME field.
– OE first deassertion time is controlled by the GPMC_CONFIG3_i[15-13] OEAADMUXOFFTIME
field.
– OE second assertion time is controlled by the GPMC_CONFIG4_i[3-0] OEONTIME field.
– OE second deassertion time is controlled by the GPMC_CONFIG4_i[12-8] OEOFFTIME field.
After a read operation, if no other access (read or write) is pending, the data bus is driven with the
previous read value. See
SPRUGX9 – 15 April 2011
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Preliminary
Section
5.2.4.9.10.
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Architecture
589
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