Texas Instruments TMS320C6A816 Series Technical Reference Manual page 740

C6-integra dsp+arm processors
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Registers
Table 6-38. System Control Register 1 (SYS_CTRL1) Field Descriptions (continued)
Bit
Field
3
Reserved
2
BSEL
1
EDGE
0
PD
740
High-Definition Multimedia Interface (HDMI)
Preliminary
Value
Description
0
Reserved
Input bus select
0
12-bit Data Bus
1
24-bit Data Bus
Edge select
0
Latch Input on Falling Edge
1
Latch Input on Rising Edge
Power down mode
HIGH is normal operation. When LOW, interrupts are in power-down mode. Most other register
values are not affected by assertion of the PD bit.
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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