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•
In Inactive mode, all internal clock paths are gated.
•
In Disabled mode, all internal clock paths not used for the system interface are gated. All GPIO
registers are accessible synchronously with the interface clock.
4.2.2.3
Sleep Mode Request and Acknowledge
Upon a Sleep mode request issued by the host processor, the GPIO module goes to the Idle mode
according to the IDLEMODE field in the system configuration register (GPIO_SYSCONFIG).
•
IDLEMODE = 0 (Force-Idle mode): the GPIO goes in Inactive mode independently of the internal
module state and the Idle acknowledge is unconditionally sent. In Force-Idle mode, the module is in
Inactive mode.
•
IDLEMODE = 1h (No-Idle mode): the GPIO does not go to the Idle mode and the Idle acknowledge
is never sent.
•
IDLEMODE = 2h (Smart-Idle mode) or IDLEMODE = 3h (Smart-Idle mode): the GPIO module
evaluates its internal capability to have the interface clock switched off. Once there is no more
internal activity (the data input register completed to capture the input GPIO pins, there is no
pending interrupt, all interrupt status bits are cleared, and there is no write access to
GPIO_DEBOUNCINGTIME register pending to be synchronized), the Idle acknowledge is asserted
and the GPIO enters Idle mode. When the system is awake, the Idle Request goes inactive, the Idle
acknowledge signals are immediately de-asserted.
NOTE: Idle mode request and Idle acknowledge are system interface sideband signals. Once
the GPIO acknowledges the Sleep mode request (Idle acknowledge has been sent), the
interface clock can be stopped anytime.
Upon a Sleep mode request issued by the host processor, the GPIO module goes to the
Idle mode only if there is no active bit in GPIO_IRQSTATUS_RAW_n registers.
4.2.2.4
Reset
The OCP hardware Reset signal has a global reset action on the GPIO. All configuration registers, all
DFFs clocked with the Interface clock or Debouncing clock and all internal state machines are reset
when the OCP hardware Reset is active (low level). The RESETDONE bit in the system status register
(GPIO_SYSSTATUS) monitors the internal reset status: it is set when the Reset is completed on both
OCP and Debouncing clock domains. The software Reset (SOFTRESET bit in the system configuration
register) has the same effect as the OCP hardware Reset signal, and the RESETDONE bit in
GPIO_SYSSTATUS is updated in the same condition.
4.2.3 Interrupt Features
4.2.3.1
Functional Description
In order to generate an interrupt request to a host processor upon a defined event (level or logic
transition) occurring on a GPIO pin, the GPIO configuration registers have to be programmed as
follows:
•
Interrupts for the GPIO channel must be enabled in the GPIO_IRQSTATUS_SET_0 and/or
GPIO_IRQSTATUS_SET_1 registers.
•
The expected event(s) on input GPIO to trigger the interrupt request has to be selected in the
GPIO_LEVELDETECT0, GPIO_LEVELDETECT1, GPIO_RISINGDETECT, and
GPIO_FALLINGDETECT registers.
For instance, interrupt generation on both edges on input k is configured by setting to 1 the kth bit in
registers GPIO_RISINGDETECT and GPIO_FALLINGDETECT along with the interrupt enabling for one
or both interrupt lines (GPIO_IRQSTATUS_SET_n).
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
General-Purpose I/O (GPIO) Interface
Architecture
531
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