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Architecture
The wait transition pin detector must be cleared before any transition detection. This is done by writing
1 to the WAITxEDGEDETECTIONSTATUS bit (x = 0 or 1) of the GPMC_IRQSTATUS register
according to the gpmc_wait pin used for the NAND device-ready signal monitoring. To detect a
wait-to-no-wait transition, the transition detector requires a wait active time detection of a minimum of
two GPMC_FCLK cycles. Software must incorporate precautions to clear the wait transition pin detector
before wait (busy) time completes.
A wait-to-no-wait transition detection can issue a GPMC interrupt if the
WAITxEDGEDETECTIONENABLE bit in the GPMC_IRQENABLE register is set and if the
WAITxEDGEDETECTIONSTATUS bit field in the GPMC_IRQSTATUS register is set.
The WAITMONITORINGTIME field does not affect wait-to-no-wait transition time detection.
It is also possible to poll the WAITxEDGEDETECTIONSTATUS bit field in the GPMC_IRQSTATUS
register according to the gpmc_wait pin used for the NAND device ready signal monitoring.
5.2.4.12.3 ECC Calculator
The General Purpose Memory Controller includes an Error Code Correction (ECC) calculator circuitry
that enables on the fly ECC calculation during data read or data program (that is, write) operations. The
page size supported by the ECC calculator in one calculation/context is 512 bytes.
The user can choose from two different algorithms with different error correction capabilities through the
GPMC_ECC_CONFIG[16] ECCALGORITHM bit:
•
Hamming code for 1-bit error code correction on 8- or 16-bit NAND Flash organized with page size
greater than 512 bytes
•
BCH (Bose-Chaudhurl-Hocquenghem) code for 4- to 16-bit error correction
The GPMC does not directly handle the error code correction itself. During writes, the GPMC computes
parity bits. During reads, the GPMC provides enough information for the processor to correct errors
without reading the data buffer all over again.
The Hamming code ECC is based on a 2-dimensional (row and column) bit parity accumulation. This
parity accumulation is either accomplished on the programmed number of bytes or 16-bit words read
from the memory device, or written to the memory device in stream mode.
Because the ECC engine includes only one accumulation context, it can be allocated to only one
chip-select at a time through the GPMC_ECC_CONFIG[3-1] ECCCS bit field. Even if two CS use
different ECC algorithms, one the Hamming code and the other a BCH code, they must define separate
ECC contexts because some of the ECC registers are common to all types of algorithms.
5.2.4.12.3.1 Hamming Code
All references to Error Code Correction (ECC) in this subsection refer to the 1-bit error correction
Hamming code.
The ECC is based on a two-dimensional (row and column) bit parity accumulation known as Hamming
Code. The parity accumulation is done for a programmed number of bytes or 16-bit word read from the
memory device or written to the memory device in stream mode.
There is no automatic error detection or correction, and it is the software NAND driver responsibility to
read the multiple ECC calculation results, compare them to the expected code value, and take the
appropriate corrective actions according to the error handling strategy (ECC storage in spare byte, error
correction on read, block invalidation).
The ECC engine includes a single accumulation context. It can be allocated to a single designated
chip-select at a time and parallel computations on different chip-selects are not possible. Since it is
allocated to a single chip-select, the ECC computation is not affected by interleaved GPMC accesses to
other chip-selects and devices. The ECC accumulation is sequentially processed in the order of data
read from or written to the memory on the designated chip-select. The ECC engine does not
differentiate read accesses from write accesses and does not differentiate data from command or
status information. It is the software responsibility to make sure only relevant data are passed to the
NAND flash memory while the ECC computation engine is active.
608
General-Purpose Memory Controller (GPMC)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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