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Architecture
Any access attempted to a nonvalid GPMC address region (CSVALID disabled or address decoding
outside a valid chip-select region) is not propagated to the external interface and a GPMC access error
is posted. In case of chip-selects overlapping, an error is generated and no access will occur on either
chip-select. Chip-select 0 is the only chip-select region enabled after either a power-up or a GPMC
reset.
Although the GPMC interface can drive up to 8 chip-selects, the frequency specified for this interface is
for a specific load. If this load is exceeded, the maximum frequency cannot be reached. One solution is
to implement a board with buffers, to allow the slowest device to maintain the total load on the lines.
5.2.4.8.2 Access Protocol
5.2.4.8.2.1 Supported Devices
The access protocol of each chip-select can be independently specified through the
GPMC_CONFIG1_i[11-10] DEVICETYPE parameter (where i = 0 to 7) for:
•
Random-access synchronous or asynchronous memory like NOR flash, SRAM
•
NAND flash asynchronous devices
For more information about the NAND flash GPMC basic programming model and NAND support, see
Section 5.2.4.12
and
5.2.4.8.2.2 Access Size Adaptation and Device Width
Each chip-select can be independently configured through the GPMC_CONFIG1_i[13-12] DEVICESIZE
field (i = 0 to 7) to interface with a 16-bit wide device or an 8-bit wide device. System requests with data
width greater than the external device data bus width are split into successive accesses according to
both the external device data-bus width and little-endian data organization.
The device does not provide the A0 byte address line required for random-byte addressable 8-bit wide
device interfacing (for both multiplexed and nonmultiplexed protocol). It limits the use of 8-bit wide
device interfacing to byte-alias accesses. This limitation is not applicable to NAND device interfacing
(8-bit wide or 16-bit wide devices).
5.2.4.8.2.3 Address/Data-Multiplexing Interface
For random synchronous or asynchronous memory interfacing (DEVICETYPE = 0b00), an address-
and data-multiplexing protocol can be selected through the GPMC_CONFIG1_i[[9-8] MUXADDDATA bit
field (i = 0 to 7). The ADV signal must be used as the external device address latch control signal. For
the associated chip-select configuration, ADV assertion and deassertion time and OE assertion time
must be set to the appropriate value to meet the address latch setup/hold time requirements of the
external device (see
This address/data-multiplexing interface is not applicable to NAND device interfacing. NAND devices
require a specific address, command, and data multiplexing protocol (see
5.2.4.8.3 External Signals
5.2.4.8.3.1 WAIT Pin Monitoring Control
GPMC access time can be dynamically controlled using an external gpmc_wait pin when the external
device access time is not deterministic and cannot be defined and controlled only using the GPMC
internal RDACCESSTIME, WRACCESSTIME and PAGEBURSTACCESSTIME wait state generator.
The GPMC features two input wait pin:gpmc_wait1, and gpmc_wait0. This pin allow control of external
devices with different wait-pin polarity. They also allow the overlap of wait-pin assertion from different
devices without affecting access to devices for which the wait pin is not asserted.
•
The GPMC_CONFIG1_i[17-16] WAITPINSELECT bit field (where i = 0 to 7) selects which input
gpmc_wait pin is used for the device attached to the corresponding chip-select.
564
General-Purpose Memory Controller (GPMC)
Preliminary
Section
5.2.4.12.1.
Section
5.2.3).
© 2011, Texas Instruments Incorporated
www.ti.com
Section
5.2.4.12).
SPRUGX9 – 15 April 2011
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