Texas Instruments TMS320C6A816 Series Technical Reference Manual page 685

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Table 5-76. GPMC_PREFETCH_CONFIG1 Field Descriptions (continued)
Bit Field
14-8 FIFOTHRESHOLD
7 ENABLEENGINE
6 Reserved
5-4 WAITPINSELECTOR
3 SYNCHROMODE
2 DMAMODE
1 Reserved
0 ACCESSMODE
SPRUGX9 – 15 April 2011
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Preliminary
Value Description
Selects the maximum number of bytes read from the FIFO or written to the FIFO
by the host on a DMA or interrupt request
0 0 byte
1h 1 byte
⋮ ⋮
40h 64 bytes
Enables the Prefetch Postwite engine
0 Prefetch Postwrite engine is disabled
1 Prefetch Postwrite engine is enabled
0 Reserved
Select which WAIT pin edge detector should start the engine in synchronized
mode
0 Selects Wait0EdgeDetection
1h Selects Wait1EdgeDetection
2h Reserved
3h Reserved
Selects when the engine starts the access to CS
0 Engine starts the access to CS as soon as STARTENGINE is set
1 Engine starts the access to CS as soon as STARTENGINE is set AND wait to
non wait edge detection on the selected wait pin
Selects interrupt synchronization or DMA request synchronization
0 Interrupt synchronization is enabled. Only interrupt line will be activated on FIFO
threshold crossing.
1 DMA request synchronization is enabled. A DMA request protocol is used.
0 Reserved
Selects pre-fetch read or write posting accesses
0 Prefetch read mode
1 Write-posting mode
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Registers
685