Texas Instruments TMS320C6A816 Series Technical Reference Manual page 466

Registers
Table 3-25. Ethernet Media Access Controller (EMAC) Registers (continued)
Offset Acronym
164h MACSTATUS
168h EMCONTROL
16Ch FIFOCONTROL
170h MACCONFIG
174h SOFTRESET
1D0h MACSRCADDRLO
1D4h MACSRCADDRHI
1D8h MACHASH1
1DCh MACHASH2
1E0h BOFFTEST
1E4h TPACETEST
1E8h RXPAUSE
1ECh TXPAUSE
500h MACADDRLO
504h MACADDRHI
508h MACINDEX
600h TX0HDP
604h TX1HDP
608h TX2HDP
60Ch TX3HDP
610h TX4HDP
614h TX5HDP
618h TX6HDP
61Ch TX7HDP
620h RX0HDP
624h RX1HDP
628h RX2HDP
62Ch RX3HDP
630h RX4HDP
634h RX5HDP
638h RX6HDP
63Ch RX7HDP
640h TX0CP
644h TX1CP
648h TX2CP
64Ch TX3CP
650h TX4CP
654h TX5CP
658h TX6CP
65Ch TX7CP
660h RX0CP
664h RX1CP
668h RX2CP
66Ch RX3CP
670h RX4CP
674h RX5CP
466 EMAC/MDIO Module
Preliminary
Register Description
MAC Status Register
Emulation Control Register
FIFO Control Register
MAC Configuration Register
Soft Reset Register
MAC Source Address Low Bytes Register
MAC Source Address High Bytes Register
MAC Hash Address Register 1
MAC Hash Address Register 2
Back Off Test Register
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
Transmit Pause Timer Register
MAC Address Low Bytes Register, Used in Receive Address
Matching
MAC Address High Bytes Register, Used in Receive Address
Matching
MAC Index Register
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
Transmit Channel 0 Completion Pointer Register
Transmit Channel 1 Completion Pointer Register
Transmit Channel 2 Completion Pointer Register
Transmit Channel 3 Completion Pointer Register
Transmit Channel 4 Completion Pointer Register
Transmit Channel 5 Completion Pointer Register
Transmit Channel 6 Completion Pointer Register
Transmit Channel 7 Completion Pointer Register
Receive Channel 0 Completion Pointer Register
Receive Channel 1 Completion Pointer Register
Receive Channel 2 Completion Pointer Register
Receive Channel 3 Completion Pointer Register
Receive Channel 4 Completion Pointer Register
Receive Channel 5 Completion Pointer Register
© 2011, Texas Instruments Incorporated
www.ti.com
Section
Section 3.3.2.30
Section 3.3.2.31
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SPRUGX9 – 15 April 2011
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