Video Mode1 Register (Vid_Mode); Video Mode1 Register (Vid_Mode) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
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Registers

6.3.2.48 Video Mode1 Register (VID_MODE)

The video mode1 register is shown in
31
15
7
6
DITHER_MODE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-79. Video Mode1 Register (VID_MODE) Field Descriptions
Bit
Field
31-8
Reserved
7-6
DITHER_MODE
5
DITHER
4
RANGE
3
CSC
2
UPSMP
1
DEMUX
0
SYNCEX
764
High-Definition Multimedia Interface (HDMI)
Preliminary
Figure 6-70
Figure 6-70. Video Mode1 Register (VID_MODE)
Reserved
R-0h
Reserved
R-0h
5
4
DITHER
RANGE
R/W
R/W
Value
Description
0
Reserved
Identifies the number of bits per output video channel:
0b00
Dither to 8 bits
0b01
Dither to 10 bits
0b10
Dither to 12 bits
0b11
Reserved
0
Dither disabled; the video output is truncated to the output width specified in DITHER_MODE
[7:6]
1
Dither enabled; the video output is dithered to the output width specified in DITHER_MODE
[7:6]
Data range 16–235 to 0–255 expansion
0
Disabled
1
Enabled.
When this bit is set, the HDMI transmitter expands the range of pixel data values from
16-235 into the full 8-bit range of 0-255. This is suitable for translating input YCbCr data into
output RGB data in PC modes that use the complete range. The HDMI Specification allows
one non-CEA-861D mode in the first and only 18-byte descriptor of the Sink's EDID 1.3. This
is the native resolution of the Sink, which may be RGB. It may be a standard PC resolution
(XGA, SXGA, WXGA, and so on), or a specific native resolution. In these cases (or for a
Sink with the Type B HDMI connector, which allows multiple PC modes), when the HDMI
transmitter receives YCbCr data, the data must be expanded to full range for outputting RGB
full-range modes.
YcbCr to RGB color space conversion
0
Disabled
1
Enabled
Upsampling 4:2:2 to 4:4:4
0
Disabled
1
Enabled
One- to two-data-channel demux
0
Disabled
1
Enabled
Embedded sync extraction
0
Disabled
1
Enabled
© 2011, Texas Instruments Incorporated
and described in
Table
6-79.
3
2
CSC
UPSMP
R/W
R/W
www.ti.com
16
8
1
0
DEMUX
SYNCEX
R/W
R/W
SPRUGX9 – 15 April 2011
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