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Registers
Table 6-23. Interrupt Disable Register (HDMI_WP_IRQENABLE_CLEAR) Field Descriptions (continued)
Bit
Field
0
ENABLE_CLEAR_CORE_INTR
726
High-Definition Multimedia Interface (HDMI)
Preliminary
Value
Description
R0
Interrupt disabled
W0
No action
R1
Interrupt enabled
W1
Enable interrupt
© 2011, Texas Instruments Incorporated
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SPRUGX9 – 15 April 2011
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