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5.2.4.12.4.1 General Facts About the Engine Configuration
The engine can be configured only if the GPMC_PREFETCH_CONTROL[0] STARTENGINE bit is
de-asserted.
The engine must be correctly configured in prefetch or write-posting mode and must be linked to a
NAND chip-select before it can be started. The chip-select is linked using the
GPMC_PREFETCH_CONFIG1[26-24] ENGINECSSELECTOR field.
In both prefetch and write-posting modes, the engine respectivelly uses byte or 16-bit word access
requests for an 8- or 16-bit wide NAND device attached to the linked chip-select. The
FIFOTHRESHOLD and TRANSFERCOUNT fields must be programmed accordingly as a number of
bytes or a number of 16-bit word.
When the GPMC_PREFETCH_CONFIG1[7] ENABLEENGINE bit is set, the FIFO entry on the L3
interconnect port side is accessible at any address in the associated chip-select memory region. When
the ENABLEENGINE bit is set, any host access to this chip-select is rerouted to the FIFO input. Directly
accessing the NAND device linked to this chip-select from the host is still possible through these
registers (where i = 0 to 7):
•
GPMC_NAND_COMMAND_i
•
GPMC_NAND_ADDRESS_i
•
GPMC_NAND_DATA_i
The FIFO entry on the L3 interconnect port can be accessed with Byte, 16-bit word, or 32-bit word
access size, according to little-endian format, even though the FIFO input is 32-bit wide.
The FIFO control is made easier through the use of interrupts or DMA requests associated with the
FIFOTHRESHOLD bit field. The GPMC_PREFETCH_STATUS[30-24] FIFOPOINTER field monitors the
number of available bytes to be read in prefetch mode or the number of free empty slots which can be
written in write-posting mode. The GPMC_PREFETCH_STATUS[13-0] COUNTVALUE field monitors
the number of remaining bytes to be read or written by the engine according to the TRANSFERCOUNT
value. The FIFOPOINTER and COUNTVALUE bit fields are always expressed as a number of bytes
even if a 16-bit wide NAND device is attached to the linked chip-select.
In prefetch mode, when the FIFOPOINTER equals 0, that is, the FIFO is empty, a host read access
receives the byte last read from the FIFO as its response. In case of 32-bit word or 16-bit word read
accesses, the last byte read from the FIFO is copied the required number of times to fit the requested
word size. In write-posting mode, when the FIFOPOINTER equals 0, that is, the FIFO is full, a host
write overwrites the last FIFO byte location. There is no underflow or overflow error reporting in the
GPMC.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Architecture
627
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