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Host byte read and write access requests to a 16-bit wide NAND device are completed as 16-bit
accesses on the device itself, because there is no byte-addressing capability on 16-bit wide NAND
devices. This means that the NAND device address pointer is incremented on a 16-bit word basis and
not on a byte basis. For a read access, only the requested byte is given back to the host, but the
remaining byte is not stored or saved by the GPMC, and the next byte or 16-bit word read access gets
the next 16-bit word NAND location. For a write access, the invalid byte part of the 16-bit word is driven
to FF, and the next byte or 16-bit word write access programs the next 16-bit word NAND location.
Generally, byte access to a 16-bit wide NAND device should be avoided, especially when ECC
calculation is enabled. 8-bit or 16-bit ECC-based computations are corrupted by a byte read to a 16-bit
wide NAND device, because the nonrequested byte is considered invalid on a read access (not
captured on the external data bus; FF is fed to the ECC engine) and is set to FF on a write access.
Host requests (read/write) issued in the chip-select memory region are translated in successive single
or split accesses (read/write) to the attached device. Therefore, incrementing 32-bit burst requests are
translated in multiple 32-bit sequential accesses following the access adaptation of the 32-bit to 8- or
16-bit device.
5.2.4.12.2 NAND Device-Ready Pin
The NAND memory device provides a ready pin to indicate data availability after a block/page opening
and to indicate that data programming is complete. The ready pin can be connected to one of the WAIT
GPMC input pins; data read accesses must not be tried when the ready pin is sampled inactive (device
is not ready) even if the associated chip-select WAITREADMONITORING bit field is set. The duration
of the NAND device busy state after the block/page opening is so long (up to 50 µs) that accesses
occurring when the ready pin is sampled inactive can stall GPMC access and eventually cause a
system time-out.
If a read access to a NAND flash is done using the wait monitoring mode, the device is blocked during
a page opening, and so is the GPMC. If the correct settings are used, other chip-selects can be used
while the memory processes the page opening command.
To avoid a time-out caused by a block/page opening delay in NAND flash, disable the wait pin
monitoring for read and write accesses (that is, set the GPMC_CONFIG1_i[[21]
WAITWRITEMONITORING and GPMC_CONFIG1_i[[22] WAITREADMONITORING bits to 0, where i =
0 to 7), and use one of the following methods instead:
•
Use software to poll the WAITnSTATUS bit (n = 0 to 1) of the GPMC_STATUS register.
•
Configure an interrupt that is generated on the WAIT signal change (through the
GPMC_IRQENABLE [11-8]bits).
Even if the READWAITMONITORING bit is not set, the external memory nR/B pin status is captured in
the programmed WAIT bit in the GPMC_STATUS register.
The READWAITMONITORING bit method must be used for other memories than NAND flash, if they
require the use of a WAIT signal.
5.2.4.12.2.1 Ready Pin Monitored by Software Polling
The ready signal state can be monitored through the GPMC_STATUS WAITxSTATUS bit (x = 0 or 1).
The software must monitor the ready pin only when the signal is declared valid. Refer to the NAND
device timing parameters to set the correct software temporization to monitor ready only after the
invalid window is complete from the last read command written to the NAND device.
5.2.4.12.2.2 Ready Pin Monitored by Hardware Interrupt
Each gpmc_wait input pin can generate an interrupt when a wait-to-no-wait transition is detected.
Depending on whether the GPMC_CONFIG WAITxPINPOLARITY bits (x = 0 or 1) is active low or
active high, the wait-to-no-wait transition is a low-to-high external WAIT signal transition or a high-to-low
external WAIT signal transition, respectively.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Architecture
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