Texas Instruments TMS320C6A816 Series Technical Reference Manual page 620

C6-integra dsp+arm processors
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Architecture
5.2.4.12.3.2.11 Mode 0x7
Page processing sequence:
Repeat with buffer 0 to S-1
– 512-byte data, processing ON
One time with buffer 0
– size0 nibbles spare, processing ON
Repeat S times (no buffer used)
– size1 nibbles spare, processing OFF
Checksum: Spare area size (nibbles) = size0 + (S - size1)
5.2.4.12.3.2.12 Mode 0x8
Page processing sequence:
Repeat with buffer 0 to S-1
– 512-byte data, processing ON
One time with buffer 0
– size0 nibbles spare, processing ON
Repeat with buffer 0 to S-1
– 1 nibble padding spare, processing OFF
– size1 nibbles spare, processing ON
Checksum: Spare area size (nibbles) = size0 + (S - (1+size1))
5.2.4.12.3.2.13 Mode 0x4
Page processing sequence:
Repeat with buffer 0 to S-1
– 512-byte data, processing ON
One time (no buffer used)
– size0 nibbles spare, processing OFF
Repeat with buffer 0 to S-1
– size1 nibbles spare, processing ON
Checksum: Spare area size (nibbles) = size0 + (S - size1)
5.2.4.12.3.2.14 Mode 0x9
Page processing sequence:
Repeat with buffer 0 to S-1
– 512-byte data, processing ON
One time (no buffer used)
– size0 nibbles spare, processing OFF
Repeat with buffer 0 to S-1
– 1 nibble padding spare, processing OFF
– size1 nibbles spare, processing ON
Checksum: Spare area size (nibbles) = size0 + (S - (1+size1))
620
General-Purpose Memory Controller (GPMC)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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