Texas Instruments TMS320C6A816 Series Technical Reference Manual page 467

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Table 3-25. Ethernet Media Access Controller (EMAC) Registers (continued)
Offset Acronym
678h RX6CP
67Ch RX7CP
200h RXGOODFRAMES
204h RXBCASTFRAMES
208h RXMCASTFRAMES
20Ch RXPAUSEFRAMES
210h RXCRCERRORS
214h RXALIGNCODEERRORS
218h RXOVERSIZED
21Ch RXJABBER
220h RXUNDERSIZED
224h RXFRAGMENTS
228h RXFILTERED
22Ch RXQOSFILTERED
230h RXOCTETS
234h TXGOODFRAMES
238h TXBCASTFRAMES
23Ch TXMCASTFRAMES
240h TXPAUSEFRAMES
244h TXDEFERRED
248h TXCOLLISION
24Ch TXSINGLECOLL
250h TXMULTICOLL
254h TXEXCESSIVECOLL
258h TXLATECOLL
25Ch TXUNDERRUN
260h TXCARRIERSENSE
264h TXOCTETS
268h FRAME64
26Ch FRAME65T127
270h FRAME128T255
274h FRAME256T511
278h FRAME512T1023
27Ch FRAME1024TUP
280h NETOCTETS
284h RXSOFOVERRUNS
288h RXMOFOVERRUNS
28Ch RXDMAOVERRUNS
SPRUGX9 – 15 April 2011
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Preliminary
Register Description
Receive Channel 6 Completion Pointer Register
Receive Channel 7 Completion Pointer Register
Network Statistics Registers
Good Receive Frames Register
Broadcast Receive Frames Register
Multicast Receive Frames Register
Pause Receive Frames Register
Receive CRC Errors Register
Receive Alignment/Code Errors Register
Receive Oversized Frames Register
Receive Jabber Frames Register
Receive Undersized Frames Register
Receive Frame Fragments Register
Filtered Receive Frames Register
Receive QOS Filtered Frames Register
Receive Octet Frames Register
Good Transmit Frames Register
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
Transmit and Receive 64 Octet Frames Register
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to RXMAXLEN Octet Frames Register
Network Octet Frames Register
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Overruns Register
© 2011, Texas Instruments Incorporated
Registers
Section
Section 3.3.2.49
Section 3.3.2.49
Section 3.3.2.50.1
Section 3.3.2.50.2
Section 3.3.2.50.3
Section 3.3.2.50.4
Section 3.3.2.50.5
Section 3.3.2.50.6
Section 3.3.2.50.7
Section 3.3.2.50.8
Section 3.3.2.50.9
Section 3.3.2.50.10
Section 3.3.2.50.11
Section 3.3.2.50.12
Section 3.3.2.50.13
Section 3.3.2.50.14
Section 3.3.2.50.15
Section 3.3.2.50.16
Section 3.3.2.50.17
Section 3.3.2.50.18
Section 3.3.2.50.19
Section 3.3.2.50.20
Section 3.3.2.50.21
Section 3.3.2.50.22
Section 3.3.2.50.23
Section 3.3.2.50.24
Section 3.3.2.50.25
Section 3.3.2.50.26
Section 3.3.2.50.27
Section 3.3.2.50.28
Section 3.3.2.50.29
Section 3.3.2.50.30
Section 3.3.2.50.31
Section 3.3.2.50.32
Section 3.3.2.50.33
Section 3.3.2.50.34
Section 3.3.2.50.35
Section 3.3.2.50.36
467
EMAC/MDIO Module