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Architecture
The memory device maximum-length burst (configured in fixed-length burst wrap or nonwrap mode)
usually corresponds to the memory device data buffer size. Memory devices with a minimum of 16
half-word buffers are the most appropriate (especially with wrap support), but memory devices with
smaller buffer size (4 or 8) are also supported, assuming that the GPMC_CONFIG1_i[24-23]
ATTACHEDDEVICEPAGELENGTH field is set accordingly to 4 or 8 words.
The device system issues only requests with addresses or starting addresses for nonwrapping burst
requests; that is, the request size boundary is aligned. In case of an eight-word-wrapping burst, the
wrapping address always occurs on the eight-words boundary. As a consequence, all words requested
must be available from the memory data buffer when the buffer size is equal to or greater than the
ATTACHEDDEVICEPAGELENGTH value. This usually means that data can be read from or written to
the buffer at a constant rate (number of cycles between data) without wait states between data
accesses. If the memory does not behave this way (nonzero wait state burstable memory), wait-pin
monitoring must be enabled to dynamically control data-access completion within the burst.
When the system burst request length is less than the ATTACHEDDEVICEPAGELENGTH value, the
GPMC proceeds with the required accesses.
5.2.4.11 pSRAM Access Specificities
pSRAM devices are SRAM-pin-compatible low-power memories that contain a self-refreshed DRAM
memory array. The GPMC_CONFIG1_i[[11-10] DEVICETYPE field (i = 0 to 3) shall be cleared to 0b00.
The pSRAM devices uses the NOR protocol. It support the following operations:
•
Asynchronous single read
•
Asynchronous page read
•
Asynchronous single write
•
Synchronous single read and write
•
Synchronous burst read
•
Synchronous burst write (not supported by NOR Flash memory)
pSRAM devices must be powered up and initialized in a predefined manner according to the
specifications of the attached device.
pSRAM devices can be programmed to use either mode: fixed or variable latency. pSRAM devices can
either automatically schedule autorefresh operations, which force the GPMC to use its WAIT signal
capability when read or write operations occur during an internal self-refresh operation, or pSRAM
devices automatically include the autorefresh operation in the access time. These devices do not
require additional WAIT signal capability or a minimum CS high pulse width between consecutive
accesses to ensure that the correct internal refresh operation is scheduled.
5.2.4.12 NAND Access Description
NAND (8-bit and 16-bit) memory devices using a standard NAND asynchronous
address/data-multiplexing scheme can be supported on any chip-select with the appropriate
asynchronous configuration settings
As for any other type of memory compatible with the GPMC interface, accesses to a chip-select
allocated to a NAND device can be interleaved with accesses to chip-selects allocated to other external
devices. This interleaved capability limits the system to chip enable don't care NAND devices, because
the chip-select allocated to the NAND device must be de-asserted if accesses to other chip-selects are
requested.
5.2.4.12.1 NAND Memory Device in Byte or 16-Bit Word Stream Mode
NAND devices require correct command and address programming before data array read or write
accesses. The GPMC does not include specific hardware to translate a random address system
request into a NAND-specific multiphase access. In that sense, GPMC NAND support, as opposed to
random memory-map device support, is data-stream-oriented (byte or 16-bit word).
600
General-Purpose Memory Controller (GPMC)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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