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Architecture
GPMC_CLK which is sent to the memory device for synchronization with the GPMC controller, is
internally retimed to correctly latch the returned data. GPMC_CONFIG5_i[4-0] RDCYCLETIME must be
greater than RDACCESSTIME in order to let the GPMC latch the last return data using the internally
retimed GPMC_CLK.
The external WAIT signal can be used in conjunction with RDACCESSTIME to control the effective
GPMC data-capture GPMC_FCLK edge on read access in both asynchronous mode and synchronous
mode. For details about wait monitoring, see
5.2.4.9.8.2 Access Time on Write Access
In asynchronous write mode, the GPMC_CONFIG6_i[[28-24] WRACCESSTIME timing parameter is not
used to define the effective write access time. Instead, it is used as a WAIT invalid timing window, and
must be set to a correct value so that the gpmc_wait pin is at a valid state two GPMC_CLK cycles
before WRACCESSTIME completes. For details about wait monitoring, see
In synchronous write mode , for single or burst accesses, WRACCESSTIME defines the number of
GPMC_FCLK cycles from start access time to the GPMC_CLK rising edge used by the memory device
for the first data capture.
The external WAIT signal can be used in conjunction with WRACCESSTIME to control the effective
memory device data capture GPMC_CLK edge for a synchronous write access. For details about wait
monitoring, see
Section
5.2.4.9.9 Page Burst Access Time (PAGEBURSTACCESSTIME)
GPMC_CONFIG5_i[27-24] PAGEBURSTACCESSTIME bit field (i = 0 to 7) can be set with a granularity
of 1 or 2 throught the GPMC_CONFIG1_i[[4] TIMEPARAGRANULARITY.
5.2.4.9.9.1 Page Burst Access Time on Read Access
In asynchronous page read mode, the delay between successive word captures in a page is controlled
through the PAGEBURSTACCESSTIME bit field. The PAGEBURSTACCESSTIME parameter must be
programmed to the rounded greater value (in GPMC_FCLK cycles) of the read access time of the
attached device.
In synchronous burst read mode, the delay between successive word captures in a burst is controlled
through the PAGEBURSTACCESSTIME field.
The external WAIT signal can be used in conjunction with PAGEBURSTACCESSTIME to control the
effective GPMC data capture GPMC_FCLK edge on read access. For details about wait monitoring,
see
Section
5.2.4.8.1.
5.2.4.9.9.2 Page Burst Access Time on Write Access
Asynchronous page write mode is not supported. PAGEBURSTACCESSTIME is irrelevant in this case.
In synchronous burst write mode, PAGEBURSTACCESSTIME controls the delay between successive
memory device word captures in a burst.
The external WAIT signal can be used in conjunction with PAGEBURSTACCESSTIME to control the
effective memory-device data capture GPMC_CLK edge in synchronous write mode. For details about
wait monitoring, see
5.2.4.9.10 Bus Keeping Support
At the end-cycle time of a read access, if no other access is pending, the GPMC drives the bus with the
last data read after RDCYCLETIME completion time to prevent bus floating and reduce power
consumption.
After a write access, if no other access is pending, the GPMC keeps driving the data bus after
WRCYCLETIME completes with the same data to prevent bus floating and power consumption.
578
General-Purpose Memory Controller (GPMC)
Preliminary
Section
5.2.4.8.1.
Section
5.2.4.8.1.
© 2011, Texas Instruments Incorporated
5.2.4.8.1.
Section
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5.2.4.8.1.
SPRUGX9 – 15 April 2011
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