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•
Write enable signal WE
– WE assertion indicates a read cycle.
– WE assertion time is controlled by the GPMC_CONFIG4_i[19-16] WEONTIME field.
– WE deassertion time is controlled by the GPMC_CONFIG4_i[28-24] WEOFFTIME field.
The WE falling edge must not be used to control the time when the burst first data is driven in the
address/data bus because some new devices require the WE signal at low during the address
phase.
•
Direction signal DIR is OUT during the entire access.
When the GPMC generates a write access to an AAD-multiplexed device, all address bits are driven
onto the address/data bus in two separate phases. The first phase is used for the MSB address and is
qualified with OE driven low. The second phase for LSB address is qualified with OE driven high. The
address phase ends at WE assertion time.
The CS and DIR signals are controlled as detailled above.
•
Address valid signal ADV is asserted and deasserted twice during a read transaction
– ADV first assertion time is controlled by the GPMC_CONFIG3_i[[6-4] ADVAADMUXONTIME
field.
– ADV first deassertion time is controlled by the GPMC_CONFIG3_i[[26-24]
ADVAADMUXRDOFFTIME field.
– ADV second assertion time is controlled by the GPMC_CONFIG3_i[[3-0] ADVONTIME field.
– ADV second deassertion time is controlled by the GPMC_CONFIG3_i[[12-8] ADVRDOFFTIME
field.
•
Output Enable signal OE is asserted and deasserted twice during a read transaction (OE second
assertion indicates a read cycle)
– OE first assertion time is controlled by the GPMC_CONFIG4_i[[6-4] OEAADMUXONTIME field.
– OE first deassertion time is controlled by the GPMC_CONFIG4_i[15-13] OEAADMUXOFFTIME
field.
– OE second assertion time is controlled by the GPMC_CONFIG4_i[3-0] OEONTIME field.
– OE second deassertion time is controlled by the GPMC_CONFIG4_i[12-8] OEOFFTIME field.
First write data is driven by the GPMC at GPMC_CONFIG6_i[19-16] WRDATAONADMUXBUS, when in
address/data mux configuration. The next write data of the burst is driven on the bus at
WRACCESSTIME + 1 during GPMC_CONFIG5_i[27-24] PAGEBURSTACCESSTIME GPMC_FCLK
cycles. The last data of the synchronous burst write is driven until GPMC_CONFIG5_i[12-8]
WRCYCLETIME completes.
•
WRACCESSTIME is defined in the GPMC_CONFIG6_i[28-24] register.
•
The PAGEBURSTACCESSTIME parameter must be set accordingly with GPMCFCLKDIVIDER and
the memory-device internal configuration.
Total access time GPMC_CONFIG5_i[12-8] WRCYCLETIME corresponds to WRACCESSTIME plus
the address hold time from CS deassertion. In
equals WRCYCLETIME0 + WRCYCLETIME1. WRCYCLETIME0 and WRCYCLETIME1 delays are not
actual parameters and are only a graphical representation of the full WRCYCLETIME value.
After a write operation, if no other access (read or write) is pending, the data bus keeps the previous
value. See
Section
5.2.4.10.3 Asynchronous and Synchronous Accesses in Nonmultiplexed Mode
Page mode is only available in non-multiplexed mode.
•
Asynchronous single read operation on a nonmultiplexed device
•
Asynchronous single write operation on a nonmultiplexed device
•
Asynchronous multiple (page mode) read operation on a nonmultiplexed device
•
Synchronous operations on a nonmultiplexed device
SPRUGX9 – 15 April 2011
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Preliminary
5.2.4.9.10.
© 2011, Texas Instruments Incorporated
Figure 5-23
the WRCYCLETIME programmed value
General-Purpose Memory Controller (GPMC)
Architecture
595
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