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•
The polarity of the wait pin is defined through the WAITxPINPOLARITY bit of the GPMC_CONFIG
register. A wait pin configured to be active low means that low level on the WAIT signal indicates
that the data is not ready and that the data bus is invalid. When WAIT is inactive, data is valid.
The GPMC access engine can be configured per CS to monitor the wait pin of the external memory
device or not, based on the access type: read or write.
•
The GPMC_CONFIG1_i[22] WAITREADMONITORING bit defines whether the wait pin should be
monitored during read accesses or not.
•
The GPMC_CONFIG1_i[21] WAITWRITEMONITORING bit defines whether the wait pin should be
monitored during write accesses or not.
The GPMC access engine can be configured to monitor the wait pin of the external memory device
asynchronously or synchronously with the GPMC_CLK clock, depending on the access type:
synchronous or asynchronous (the GPMC_CONFIG1_i[29] READTYPE and GPMC_CONFIG1_i[27]
WRITETYPE bits).
5.2.4.8.3.2 Wait Monitoring During an Asynchronous Read Access
When wait-pin monitoring is enabled for read accesses (WAITREADMONITORING), the effective
access time is a logical AND combination of the RDACCESSTIME timing completion and the
wait-deasserted state.
During asynchronous read accesses with wait-pin monitoring enabled, the wait pin must be at a valid
level (asserted or deasserted) for at least two GPMC clock cycles before RDACCESSTIME completes,
to ensure correct dynamic access-time control through wait-pin monitoring. The advance pipelining of
the two GPMC clock cycles is the result of the internal synchronization requirements for the WAIT
signal.
In this context, RDACCESSTIME is used as a WAIT invalid timing window and is set to such a value
that the wait pin is at a valid state two GPMC clock cycles before RDACCESSTIME completes.
Similarly, during a multiple-access cycle (for example, asynchronous read page mode), the effective
access time is a logical AND combination of PAGEBURSTACCESSTIME timing completion and the
wait-deasserted state. Wait-monitoring pipelining is also applicable to multiple accesses (access within
a page).
•
WAIT monitored as active freezes the CYCLETIME counter. For an access within a page, when the
CYCLETIME counter is by definition in a lock state, WAIT monitored as asserted extends the
current access time in the page. Control signals are kept in their current state. The data bus is
considered invalid, and no data are captured during this clock cycle.
•
WAIT monitored as inactive unfreezes the CYCLETIME counter. For an access within a page, when
the CYCLETIME counter is by definition in a lock state, WAIT monitored as inactive completes the
current access time and starts the next access phase in the page. The data bus is considered valid,
and data are captured during this clock cycle. In case of a single access or if this was the last
access in a multiple-access cycle, all signals are controlled according to their related control timing
value and according to the CYCLETIME counter status.
When a delay larger than two GPMC clocks must be observed between wait-pin deactivation time and
data valid time (including the required GPMC and the device data setup time), an extra delay can be
added between wait-pin deassertion time detection and effective data-capture time and the effective
unlock of the CYCLETIME counter. This extra delay can be programmed in the
GPMC_CONFIG1_i[19-18] WAITMONITORINGTIME field (i = 0 to 7).
•
The WAITMONITORINGTIME parameter does not delay the wait-pin active or inactive detection,
nor does it modify the two GPMC clocks pipelined detection delay.
•
This extra delay is expressed as a number of GPMC_CLK clock cycles, even though the access is
defined as asynchronous, and no GPMC_CLK clock is provided to the external device. Still,
GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define
the correct WAITMONITORINGTIME delay.
Figure 5-7
shows wait behavior during an asynchronous single read access.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Architecture
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