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5.2.4.8.3.9 GPMC_DIR Pin
The GPMC_DIR pin is used to control I/O direction on the GPMC data bus GPMC_D[15-0]. Depending
on top-level pad multiplexing, this signal can be output and used externally to the device, if required.
The GPMC_DIR pin is low during transmit (OUT) and high during receive (IN).
For write accesses, the GPMC_DIR pin stays OUT from start-cycle time to end-cycle time.
For read accesses, the GPMC_DIR pin goes from OUT to IN at OE assertion time and stays IN until:
•
BUSTURNAROUND is enabled
– The GPMC_DIR pin goes from IN to OUT at end-cycle time plus programmable bus turnaround
time.
•
BUSTURNAROUND is disabled
– After an asynchronous read access, the GPMC_DIR pin goes from IN to OUT at
RDACCESSTIME + 1 GPMC_FCLK cycle or when RDCYCLETIME completes, whichever
occurs last.
– After a synchronous read access, the GPMC_DIR pin goes from IN to OUT at RDACCESSTIME
+ 2 GPMC_FCLK cycles or when RDCYCLETIME completes, whichever occurs last.
Because of the bus-keeping feature of the GPMC, after a read or write access and with no other
accesses pending, the default value of the GPMC_DIR pin is OUT (see
nonmultiplexed devices, the GPMC_DIR pin stays IN between two successive read accesses to prevent
unnecessary toggling.
5.2.4.8.3.10 Reset
No reset signal is sent to the external memory device by the GPMC. For more information about
external-device reset, see Power, Reset, and Clock Management.
The PRCM module provides an input pin, global_rst_n, to the GPMC:
•
The global_rst_n pin is activated during device warm reset and cold reset.
•
The global_rst_n pin initializes the internal state-machine and the internal configuration registers.
5.2.4.8.3.11 Write Protect Signal (WP)
When connected to the attached memory device, the write protect signal can enable or disable the
lockdown function of the attached memory. The GPMC_WP output pin value is controlled through the
GPMC_CONFIG[4] WRITEPROTECT bit, which is common to all CS.
5.2.4.8.3.12 Byte Enable (BE1/BE0)
Byte enable signals (BE1/BE0) are:
•
Valid (asserted or nonasserted according to the incoming system request) from access start to
access completion for asynchronous and synchronous single accesses
•
Asserted low from access start to access completion for asynchronous and synchronous multiple
read accesses
•
Valid (asserted or nonasserted, according to the incoming system request) synchronously to each
written data for synchronous multiple write accesses
5.2.4.8.4 Error Handling
When an error occurs in the GPMC, the error information is stored in the GPMC_ERR_TYPE register
and the address of the illegal access is stored in the GPMC_ERR_ADDRESS register. The GPMC
keeps only the first error abort information until the GPMC_ERR_TYPE register is reset. Subsequent
accesses that cause errors are not logged until the error is cleared by hardware with the
GPMC_ERR_TYPE[0]ERRORVALID bit.
•
ERRORNOTSUPPADD occurs when an incoming system request address decoding does not
match any valid chip-select region, or if two chip-select regions are defined as overlapped, or if a
register file access is tried outside the valid address range of 1KB.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Section
5.2.4.9.10). In
General-Purpose Memory Controller (GPMC)
Architecture
573
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