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Architecture
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ERRORNOTSUPPMCMD occurs when an unsupported command request is decoded at the L3
Slow interconnect interface
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ERRORTIMEOUT: A time-out mechanism prevents the system from hanging. The start value of the
9-bit time-out counter is defined in the GPMC_TIMEOUT_CONTROL register and enabled with the
GPMC_TIMEOUT_CONTROL[0] TIMEOUTENABLE bit. When enabled, the counter starts at start-cycle
time until it reaches 0 and data is not responded to from memory, and then a time-out error occurs.
When data are sent from memory, this counter is reset to its start value. With multiple accesses
(asynchronous page mode or synchronous burst mode), the counter is reset to its start value for each
data access within the burst.
The GPMC does not generate interrupts on these errors. True abort to the MPU or interrupt generation
is handled at the interconnect level.
5.2.4.9
Timing Setting
The GPMC offers the maximum flexibility to support various access protocols. Most of the timing
parameters of the protocol access used by the GPMC to communicate with attached memories or
devices are programmable on a chip-select basis. Assertion and deassertion times of control signals
are defined to match the attached memory or device timing specifications and to get maximum
performance during accesses. For more information on GPMC_CLK and GPMC_FCLK see
Section
5.2.4.9.6.
In the following sections, the start access time refer to the time at which the access begins.
5.2.4.9.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
The GPMC_CONFIG5_i[4-0] RDCYCLETIME and GPMC_CONFIG5_i[12-8] WRCYCLETIME fields (i =
0 to 7) define the address bus and byte enables valid times for read and write accesses. To ensure a
correct duty cycle of GPMC_CLK between accesses, RDCYCLETIME and WRCYCLETIME are
expressed in GPMC_FCLK cycles and must be multiples of the GPMC_CLK cycle. RDCYCLETIME and
WRCYCLETIME bit fields can be set with a granularity of 1 or 2 throught GPMC_CONFIG1_i[4]
TIMEPARAGRANULARITY.
When either RDCYCLETIME or WRCYCLETIME completes, if they are not already deasserted, all
control signals (CS, ADV_ALE, OE_RE, WE, and BE0_CLE) are deasserted to their reset values,
regardless of their deassertion time parameters.
An exception to this forced deassertion occurs when a pipelined request to the same chip-select or to a
different chip-select is pending. In such a case, it is not necessary to deassert a control signal with
deassertion time parameters equal to the cycle-time parameter. This exception to forced deassertion
prevents any unnecessary glitches. This requirement also applies to BE signals, thus avoiding an
unnecessary BE glitch transition when pipelining requests.
If no inactive cycles are required between successive accesses to the same or to a different chip-select
(GPMC_CONFIG6_i[7] CYCLE2CYCLESAMECSEN = 0 or GPMC_CONFIG6_i[6]
CYCLE2CYCLEDIFFCSEN = 0, where i = 0 to 3), and if assertion-time parameters associated with the
pipelined access are equal to 0, asserted control signals (CS, ADV_ALE, BE0_CLE, WE, and OE_RE)
are kept asserted. This applies to any read/write to read/write access combination.
If inactive cycles are inserted between successive accesses, that is, CYCLE2CYCLESAMECSEN = 1
or CYCLE2CYCLEDIFFCSEN = 1, the control signals are forced to their respective default reset values
for the number of GPMC_FCLK cycles defined in CYCLE2CYCLEDELAY.
5.2.4.9.2 CS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME /
CSWROFFTIME / CSEXTRADELAY)
The GPMC_CONFIG2_i[3-0] CSONTIME field (where i = 0 to 7) defines the CS signal-assertion time
relative to the start access time. It is common for read and write accesses.
The GPMC_CONFIG2_i[12-8] CSRDOFFTIME (read access) and GPMC_CONFIG2_i[20-16]
CSWROFFTIME (write access) bit fields define the CS signal deassertion time relative to start access
time.
574
General-Purpose Memory Controller (GPMC)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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