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5.2.4.9.6 GPMC_CLK
GPMC_CLK is the external clock provided to the attached synchronous memory or device.
•
The GPMC_CLK clock frequency is the GPMC_FCLK functional clock frequency divided by 1, 2, 3,
or 4, depending on the GPMC_CONFIG1_i[1-0] GPMCFCLKDIVIDER bit field (where i = 0 to 7),
with a guaranteed 50-percent duty cycle.
•
The GPMC_CLK clock is only activated when the access in progress is defined as synchronous
(read or write access).
•
The GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field (i = 0 to 7) defines the number of
GPMC_FCLK cycles from start access time to GPMC_CLK activation.
•
The GPMC_CLK clock is stopped when cycle time completes and is asserted low between
accesses.
•
The GPMC_CLK clock is kept low when access is defined as asynchronous.
When cycle time completes, the GPMC_CLK may be high because of the GPMCFCLKDIVIDER bit
field. To ensure correct stoppage of the GPMC_CLK clock within the 50-percent required duty cycle, it
is the user's responsibility to extend the RDCYCLETIME or WRCYCLETIME value.
To ensure a correct external clock cycle, the following rules must be applied:
•
(RDCYCLETIME CLKACTIVATIONTIME) must be a multiple of (GPMCFCLKDIVIDER + 1).
•
The PAGEBURSTACCESSTIME value must be a multiple of (GPMCFCLKDIVIDER + 1).
5.2.4.9.7 GPMC_CLK and Control Signals Setup and Hold
Control-signal transition (assertion and deassertion) setup and hold values with respect to the
GPMC_CLK edge can be controlled in the following ways:
•
For the GPMC_CLK signal, the GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field (i = 0 to 7)
allows setup and hold control of control-signal assertion time.
•
The use of a divided GPMC_CLK allows setup and hold control of control-signal assertion and
deassertion times.
•
When GPMC_CLK runs at the GPMC_FCLK frequency so that GPMC_CLK edge and control-signal
transitions refer to the same GPMC_FCLK edge, the control-signal transitions can be delayed by
half of a GPMC_FCLK period to provide minimum setup and hold times. This half-GPMC_FCLK
delay is enabled with the CSEXTRADELAY, ADVEXTRADELAY, OEEXTRADELAY, or
WEEXTRADELAY parameter. This delay must be used carefully to prevent control-signal overlap
between successive accesses to different chip-selects. This implies that the RDCYCLETIME and
WRCYCLETIME are greater than the last control-signal deassertion time, including the extra
half-GPMC_FCLK cycle.
5.2.4.9.8 Access Time (RDACCESSTIME / WRACCESSTIME)
The read access time and write access time durations can be programmed independently through
GPMC_CONFIG5_i[20-16] RDACCESSTIME and GPMC_CONFIG6_i[28-24] WRACCESSTIME (i = 0
to 7). This allows OE and GPMC data capture timing parameters to be independent of WE and memory
device data capture timing parameters. RDACCESSTIME and WRACCESSTIME bit fields can be set
with a granularity of 1 or 2 throught GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY.
5.2.4.9.8.1 Access Time on Read Access
In asynchronous read mode, for single and paged accesses, GPMC_CONFIG5_i[[20-16]
RDACCESSTIME field (i = 0 to 7) defines the number of GPMC_FCLK cycles from start access time to
the GPMC_FCLK rising edge used for the first data capture. RDACCESSTIME must be programmed to
the rounded greater value (in GPMC_FCLK cycles) of the read access time of the attached memory
device.
In synchronous read mode, for single or burst accesses, RDACCESSTIME defines the number of
GPMC_FCLK cycles from start access time to the GPMC_FCLK rising edge corresponding to the
GPMC_CLK rising edge used for the first data capture.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Architecture
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