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Architecture
6.2.9.2.4.3 L-PCM 24-bit Format Adaptation
When the audio FIFO is filled with a 24-bit sample on the 32-bit container, it is already in a format
similar to IEC 61937/IEC 60958, left- or right-justified, depending on the FIFO filling (the
HDMI_WP_AUDIO_CFG[3] JUSTIFY bit). In this case, the data in the audio FIFO is sent directly to the
HDMI core without adaptation. However, the 8 dummy bits (MSB or LSB, depending on the justification)
are filled with 0 data.
6.2.10 TXPHY Functions
6.2.10.1 TXPHY Overview
NOTE: The HDMI_TXPHY module must be configured before any transfer on the HDMI link. The
HDMI module is fully functional only when the TMDS clock is provided. It has an internal
PLL which will take in PCLK as an input and provide the required TCLK based on register
configuration.
The HDMI_TXPHY receives 30 bits of TMDS parallel encoded data from the HDMI module and then
prepares the data for transmission by serializing it. HDMI_TXPHY is a complex I/O with four
unidirectional lane modules. This includes three data lane modules and one clock lane module. Each
lane module has two data pads (DX and DY), which form a differential pair. These correspond to the
HDMI serial output transmit signals, as described in
complementary lane module on the external HDMI receiver device using a point-to-point interconnect.
The maximum data rate supported is 1.85625 Gbps per data lane. The lane module function and
position are configurable. That is, any lane module can be chosen as a clock or a data lane module,
and the DX/DY data pad for each lane module can be configured as a positive polarity (DP) or negative
polarity (DN) pin.
6.2.10.2 TXPHY Clock Domains
The HDMI_TXPHY module has the following clock domains:
•
TMDS clock domain: This is the data interface clock to the HDMI module. The data received on the
HDMI_TXPHY inputs are sampled on this clock.
•
HFBITCLK clock domain: This is the high frequency clock on which the transmit of the serialized
data occurs.
•
REFCLK clock domain: This is the 48-MHz free-running clock (DSS_HDMI) that is used as a
reference for the switched capacitor circuit.
6.2.10.3 TXPHY RX Connection Detect
The HDMI_TXPHY can detect a pullup to 3.3 V on any clock and data lines. This situation occurs when
an external HDMI receiver is connected to the device.
The information can be read by reading TMDS_CNTL2[0], RSEN.
6.2.10.4 TXPHY Data Interface
6.2.10.4.1 Input Interface
The HDMI_TXPHY module receives the 30-bit parallel data on its D0 to D2 inputs. The data is sampled
on the rising edge of the TMDS clock.
6.2.10.4.2 Output Interface
The serialized data on differential output lines DX/DY has the order LSB first and MSB last. The TMDS
clock on the clock lane has a falling edge at the start of the 10-bit serial data word on the line.
716
High-Definition Multimedia Interface (HDMI)
Preliminary
Table
6-4. The data pads are connected with a
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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