Receive Channel N Free Buffer Count Register (Rxnfreebuffer); Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Registers
3.3.2.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)
The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in
described in Table
Figure 3-53. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
31
15
LEGEND: R = Read only; WI = Write to increment; -n = value after reset
Table 3-53. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions
Bit Field
31-16 Reserved
15-0 RXnFREEBUF
490
EMAC/MDIO Module
Preliminary
3-53.
RXnFREEBUF
Value Description
0 Reserved
0-FFh Receive free buffer count. These bits contain the count of free buffers available. The
RXFILTERTHRESH value is compared with this field to determine if low priority frames should be
filtered. The RXnFLOWTHRESH value is compared with this field to determine if receive flow
control should be issued against incoming packets (if enabled). This is a write-to-increment field.
This field rolls over to 0 on overflow.
If hardware flow control or QOS is used, the host must initialize this field to the number of available
buffers (one register per channel). The EMAC decrements the associated channel register for each
received frame by the number of buffers in the received frame. The host must write this field with
the number of buffers that have been freed due to host processing.
© 2011, Texas Instruments Incorporated
Reserved
R-0
WI-0
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Figure 3-53 and
16
0
SPRUGX9 – 15 April 2011
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