Table of Contents
Advertisement
www.ti.com
Wait-monitoring pipelining definition applies to whole burst accesses:
•
WAIT monitored as active freezes the CYCLETIME counter. For accesses within a burst, when the
CYCLETIME counter is by definition in a lock state, WAIT monitored as active indicates that the
data bus is not being captured by the external device. Control signals are kept in their current state.
The data bus is kept in its current state.
•
WAIT monitored as inactive unfreezes the CYCLETIME counter. For accesses within a burst, when
the CYCLETIME counter is by definition in a lock state, WAIT monitored as inactive indicates the
effective data capture of the bus by the external device and starts the next access of the burst. In
case of a single access or if this was the last access in a multiple access cycle, all signals, including
the data bus, are controlled according to their related control timing value and the CYCLETIME
counter status.
Wait monitoring is supported for all configurations except for GPMC_CONFIG1_i[19-18]
WAITMONITORINGTIME = 0 (where i = 0 to 3) for write bursts with a clock divider of 1 or 2
(GPMC_CONFIG1_i[1-0] GPMCFCLKDIVIDER field equal to 0 or 1, respectively).
5.2.4.8.3.6 WAIT With NAND Device
For details about the use of the wait pin for communication with a NAND flash external device, see
Section
5.2.4.12.2.
5.2.4.8.3.7 Idle Cycle Control Between Successive Accesses
5.2.4.8.3.7.1 Bus Turnaround (BUSTURNAROUND)
To prevent data-bus contention, an access that follows a read access to a slow memory/device must be
delayed (in other words, control the CS/OE de-assertion to data bus in high-impedance delay).
The bus turnaround is a time-out counter starting after CS or OE de-assertion time, whichever occurs
first, and delays the next access start-cycle time. The counter is programmed through the
GPMC_CONFIG6_i[3-0] BUSTURNAROUND bit field (where i = 0 to 7).
After a read access to a chip-select with a non zero BUSTURNAROUND, the next access is delayed
until the BUSTURNAROUND delay completes, if the next access is one of the following:
•
A write access to any chip-select (same or different from the chip-select data was read from)
•
A read access to a different chip-select from the chip-select data was read access from
•
A read or write access to a chip-select associated with an address/data-multiplexed device
Bus keeping starts after bus turnaround completion so that DIR changes from IN to OUT after bus
turnaround. The bus will not have enough time to go into high-impedance even though it could be
driven with the same value before bus turnaround timing.
BUSTURNAROUND delay runs in parallel with GPMC_CONFIG6_i[3-0] CYCLE2CYCLEDELAY delays.
It should be noted that BUSTURNAROUND is a timing parameter for the ending chip-select access
while CYCLE2CYCLEDELAY is a timing parameter for the following chip-select access. The effective
minimum delay between successive accesses is driven by these delay timing parameters and by the
access type of the following access. See
Another way to prevent bus contention is to define an earlier CS or OE deassertion time for slow
devices or to extend the value of RDCYCLETIME. Doing this prevents bus contention, but affects all
accesses of this specific chip-select.
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Figure 5-9
to
Figure
© 2011, Texas Instruments Incorporated
5-11.
General-Purpose Memory Controller (GPMC)
Architecture
569
Advertisement
Table of Contents
